226 	int clock = crtc_state->port_clock;  in icl_pll_to_ddi_clk_sel()
261 static u32 ddi_buf_phy_link_rate(int port_clock)  in ddi_buf_phy_link_rate()  argument
263 	switch (port_clock) {  in ddi_buf_phy_link_rate()
281 		MISSING_CASE(port_clock);  in ddi_buf_phy_link_rate()
300 		intel_dp->DP |= ddi_buf_phy_link_rate(crtc_state->port_clock);  in intel_ddi_init_dp_buf_reg()
1023 	if (crtc_state->port_clock > 600000)  in icl_combo_phy_loadgen_select()
1219 			     crtc_state->port_clock < 300000 ? CFG_LOW_RATE_LKREN_EN : 0);  in icl_mg_phy_set_signal_levels()
1227 			     crtc_state->port_clock > 500000 ?  in icl_mg_phy_set_signal_levels()
1234 			     crtc_state->port_clock > 500000 ?  in icl_mg_phy_set_signal_levels()
2282 				 crtc_state->port_clock,  in tgl_ddi_pre_enable_dp()
2427 				 crtc_state->port_clock,  in hsw_ddi_pre_enable_dp()
3220 	if (DISPLAY_VER(dev_priv) >= 12 && crtc_state->port_clock > 594000)  in intel_ddi_compute_min_voltage_level()
3222 	else if (IS_JSL_EHL(dev_priv) && crtc_state->port_clock > 594000)  in intel_ddi_compute_min_voltage_level()
3224 	else if (DISPLAY_VER(dev_priv) >= 11 && crtc_state->port_clock > 594000)  in intel_ddi_compute_min_voltage_level()
3474 	crtc_state->port_clock = intel_dpll_get_freq(i915, crtc_state->shared_dpll,  in intel_ddi_get_clock()
3482 	crtc_state->port_clock = intel_mpllb_calc_port_clock(encoder, &crtc_state->mpllb_state);  in dg2_ddi_get_config()
3541 		crtc_state->port_clock = icl_calc_tbt_pll_link(i915, encoder->port);  in icl_ddi_tc_get_clock()
3543 		crtc_state->port_clock = intel_dpll_get_freq(i915, crtc_state->shared_dpll,  in icl_ddi_tc_get_clock()
3690 		crtc_state1->port_clock == crtc_state2->port_clock &&  in crtcs_port_sync_compatible()