| /Linux-v6.1/drivers/pci/controller/dwc/ |
| D | pcie-tegra194.c | 297 static inline void appl_writel(struct tegra_pcie_dw *pcie, const u32 value, in appl_writel() argument
300 writel_relaxed(value, pcie->appl_base + reg); in appl_writel()
303 static inline u32 appl_readl(struct tegra_pcie_dw *pcie, const u32 reg) in appl_readl() argument
305 return readl_relaxed(pcie->appl_base + reg); in appl_readl()
315 struct tegra_pcie_dw *pcie = to_tegra_pcie(pci); in apply_bad_link_workaround() local
324 val = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKSTA); in apply_bad_link_workaround()
328 if (pcie->init_link_width > current_link_width) { in apply_bad_link_workaround()
330 val = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + in apply_bad_link_workaround()
334 dw_pcie_writew_dbi(pci, pcie->pcie_cap_base + in apply_bad_link_workaround()
337 val = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + in apply_bad_link_workaround()
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| D | pcie-intel-gw.c | 82 static inline void pcie_app_wr(struct intel_pcie *pcie, u32 ofs, u32 val) in pcie_app_wr() argument
84 writel(val, pcie->app_base + ofs); in pcie_app_wr()
87 static void pcie_app_wr_mask(struct intel_pcie *pcie, u32 ofs, in pcie_app_wr_mask() argument
90 pcie_update_bits(pcie->app_base, ofs, mask, val); in pcie_app_wr_mask()
93 static inline u32 pcie_rc_cfg_rd(struct intel_pcie *pcie, u32 ofs) in pcie_rc_cfg_rd() argument
95 return dw_pcie_readl_dbi(&pcie->pci, ofs); in pcie_rc_cfg_rd()
98 static inline void pcie_rc_cfg_wr(struct intel_pcie *pcie, u32 ofs, u32 val) in pcie_rc_cfg_wr() argument
100 dw_pcie_writel_dbi(&pcie->pci, ofs, val); in pcie_rc_cfg_wr()
103 static void pcie_rc_cfg_wr_mask(struct intel_pcie *pcie, u32 ofs, in pcie_rc_cfg_wr_mask() argument
106 pcie_update_bits(pcie->pci.dbi_base, ofs, mask, val); in pcie_rc_cfg_wr_mask()
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| D | pcie-visconti.c | 97 static void visconti_ulreg_writel(struct visconti_pcie *pcie, u32 val, u32 reg) in visconti_ulreg_writel() argument
99 writel_relaxed(val, pcie->ulreg_base + reg); in visconti_ulreg_writel()
102 static u32 visconti_ulreg_readl(struct visconti_pcie *pcie, u32 reg) in visconti_ulreg_readl() argument
104 return readl_relaxed(pcie->ulreg_base + reg); in visconti_ulreg_readl()
108 static void visconti_smu_writel(struct visconti_pcie *pcie, u32 val, u32 reg) in visconti_smu_writel() argument
110 writel_relaxed(val, pcie->smu_base + reg); in visconti_smu_writel()
114 static void visconti_mpu_writel(struct visconti_pcie *pcie, u32 val, u32 reg) in visconti_mpu_writel() argument
116 writel_relaxed(val, pcie->mpu_base + reg); in visconti_mpu_writel()
119 static u32 visconti_mpu_readl(struct visconti_pcie *pcie, u32 reg) in visconti_mpu_readl() argument
121 return readl_relaxed(pcie->mpu_base + reg); in visconti_mpu_readl()
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| D | pcie-uniphier.c | 75 static void uniphier_pcie_ltssm_enable(struct uniphier_pcie *pcie, in uniphier_pcie_ltssm_enable() argument
80 val = readl(pcie->base + PCL_APP_READY_CTRL); in uniphier_pcie_ltssm_enable()
85 writel(val, pcie->base + PCL_APP_READY_CTRL); in uniphier_pcie_ltssm_enable()
88 static void uniphier_pcie_init_rc(struct uniphier_pcie *pcie) in uniphier_pcie_init_rc() argument
93 val = readl(pcie->base + PCL_MODE); in uniphier_pcie_init_rc()
96 writel(val, pcie->base + PCL_MODE); in uniphier_pcie_init_rc()
99 val = readl(pcie->base + PCL_APP_PM0); in uniphier_pcie_init_rc()
101 writel(val, pcie->base + PCL_APP_PM0); in uniphier_pcie_init_rc()
104 val = readl(pcie->base + PCL_PINCTRL0); in uniphier_pcie_init_rc()
109 writel(val, pcie->base + PCL_PINCTRL0); in uniphier_pcie_init_rc()
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| D | pcie-keembay.c | 72 static void keembay_ep_reset_assert(struct keembay_pcie *pcie) in keembay_ep_reset_assert() argument
74 gpiod_set_value_cansleep(pcie->reset, 1); in keembay_ep_reset_assert()
78 static void keembay_ep_reset_deassert(struct keembay_pcie *pcie) in keembay_ep_reset_deassert() argument
88 gpiod_set_value_cansleep(pcie->reset, 0); in keembay_ep_reset_deassert()
92 static void keembay_pcie_ltssm_set(struct keembay_pcie *pcie, bool enable) in keembay_pcie_ltssm_set() argument
96 val = readl(pcie->apb_base + PCIE_REGS_PCIE_APP_CNTRL); in keembay_pcie_ltssm_set()
101 writel(val, pcie->apb_base + PCIE_REGS_PCIE_APP_CNTRL); in keembay_pcie_ltssm_set()
106 struct keembay_pcie *pcie = dev_get_drvdata(pci->dev); in keembay_pcie_link_up() local
109 val = readl(pcie->apb_base + PCIE_REGS_PCIE_SII_PM_STATE); in keembay_pcie_link_up()
116 struct keembay_pcie *pcie = dev_get_drvdata(pci->dev); in keembay_pcie_start_link() local
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| D | pcie-qcom.c | 207 int (*get_resources)(struct qcom_pcie *pcie);
208 int (*init)(struct qcom_pcie *pcie);
209 int (*post_init)(struct qcom_pcie *pcie);
210 void (*deinit)(struct qcom_pcie *pcie);
211 void (*ltssm_enable)(struct qcom_pcie *pcie);
212 int (*config_sid)(struct qcom_pcie *pcie);
231 static void qcom_ep_reset_assert(struct qcom_pcie *pcie) in qcom_ep_reset_assert() argument
233 gpiod_set_value_cansleep(pcie->reset, 1); in qcom_ep_reset_assert()
237 static void qcom_ep_reset_deassert(struct qcom_pcie *pcie) in qcom_ep_reset_deassert() argument
241 gpiod_set_value_cansleep(pcie->reset, 0); in qcom_ep_reset_deassert()
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| D | Makefile | 2 obj-$(CONFIG_PCIE_DW) += pcie-designware.o
3 obj-$(CONFIG_PCIE_DW_HOST) += pcie-designware-host.o
4 obj-$(CONFIG_PCIE_DW_EP) += pcie-designware-ep.o
5 obj-$(CONFIG_PCIE_DW_PLAT) += pcie-designware-plat.o
8 obj-$(CONFIG_PCIE_FU740) += pcie-fu740.o
10 obj-$(CONFIG_PCIE_SPEAR13XX) += pcie-spear13xx.o
14 obj-$(CONFIG_PCIE_QCOM) += pcie-qcom.o
15 obj-$(CONFIG_PCIE_QCOM_EP) += pcie-qcom-ep.o
16 obj-$(CONFIG_PCIE_ARMADA_8K) += pcie-armada8k.o
17 obj-$(CONFIG_PCIE_ARTPEC6) += pcie-artpec6.o
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| D | pcie-armada8k.c | 74 static void armada8k_pcie_disable_phys(struct armada8k_pcie *pcie) in armada8k_pcie_disable_phys() argument
79 phy_power_off(pcie->phy[i]); in armada8k_pcie_disable_phys()
80 phy_exit(pcie->phy[i]); in armada8k_pcie_disable_phys()
84 static int armada8k_pcie_enable_phys(struct armada8k_pcie *pcie) in armada8k_pcie_enable_phys() argument
90 ret = phy_init(pcie->phy[i]); in armada8k_pcie_enable_phys()
94 ret = phy_set_mode_ext(pcie->phy[i], PHY_MODE_PCIE, in armada8k_pcie_enable_phys()
95 pcie->phy_count); in armada8k_pcie_enable_phys()
97 phy_exit(pcie->phy[i]); in armada8k_pcie_enable_phys()
101 ret = phy_power_on(pcie->phy[i]); in armada8k_pcie_enable_phys()
103 phy_exit(pcie->phy[i]); in armada8k_pcie_enable_phys()
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| /Linux-v6.1/drivers/pci/controller/ |
| D | pci-aardvark.c | 293 static inline void advk_writel(struct advk_pcie *pcie, u32 val, u64 reg) in advk_writel() argument
295 writel(val, pcie->base + reg); in advk_writel()
298 static inline u32 advk_readl(struct advk_pcie *pcie, u64 reg) in advk_readl() argument
300 return readl(pcie->base + reg); in advk_readl()
303 static u8 advk_pcie_ltssm_state(struct advk_pcie *pcie) in advk_pcie_ltssm_state() argument
308 val = advk_readl(pcie, CFG_REG); in advk_pcie_ltssm_state()
313 static inline bool advk_pcie_link_up(struct advk_pcie *pcie) in advk_pcie_link_up() argument
316 u8 ltssm_state = advk_pcie_ltssm_state(pcie); in advk_pcie_link_up()
320 static inline bool advk_pcie_link_active(struct advk_pcie *pcie) in advk_pcie_link_active() argument
330 u8 ltssm_state = advk_pcie_ltssm_state(pcie); in advk_pcie_link_active()
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| D | pcie-altera.c | 45 #define S10_RP_CFG_ADDR(pcie, reg) \ argument
46 (((pcie)->hip_base) + (reg) + (1 << 20))
47 #define S10_RP_SECONDARY(pcie) \ argument
48 readb(S10_RP_CFG_ADDR(pcie, PCI_SECONDARY_BUS))
60 #define TLP_CFG_DW0(pcie, cfg) \ argument
63 #define TLP_CFG_DW1(pcie, tag, be) \ argument
64 (((TLP_REQ_ID(pcie->root_bus_nr, RP_DEVFN)) << 16) | (tag << 8) | (be))
99 int (*tlp_read_pkt)(struct altera_pcie *pcie, u32 *value);
100 void (*tlp_write_pkt)(struct altera_pcie *pcie, u32 *headers,
102 bool (*get_link_status)(struct altera_pcie *pcie);
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| D | pcie-xilinx-nwl.c | 177 static inline u32 nwl_bridge_readl(struct nwl_pcie *pcie, u32 off) in nwl_bridge_readl() argument
179 return readl(pcie->breg_base + off); in nwl_bridge_readl()
182 static inline void nwl_bridge_writel(struct nwl_pcie *pcie, u32 val, u32 off) in nwl_bridge_writel() argument
184 writel(val, pcie->breg_base + off); in nwl_bridge_writel()
187 static bool nwl_pcie_link_up(struct nwl_pcie *pcie) in nwl_pcie_link_up() argument
189 if (readl(pcie->pcireg_base + PS_LINKUP_OFFSET) & PCIE_PHY_LINKUP_BIT) in nwl_pcie_link_up()
194 static bool nwl_phy_link_up(struct nwl_pcie *pcie) in nwl_phy_link_up() argument
196 if (readl(pcie->pcireg_base + PS_LINKUP_OFFSET) & PHY_RDY_LINKUP_BIT) in nwl_phy_link_up()
201 static int nwl_wait_for_link(struct nwl_pcie *pcie) in nwl_wait_for_link() argument
203 struct device *dev = pcie->dev; in nwl_wait_for_link()
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| D | pcie-mediatek-gen3.c | 199 struct mtk_gen3_pcie *pcie = bus->sysdata; in mtk_pcie_config_tlp_header() local
208 writel_relaxed(val, pcie->base + PCIE_CFGNUM_REG); in mtk_pcie_config_tlp_header()
214 struct mtk_gen3_pcie *pcie = bus->sysdata; in mtk_pcie_map_bus() local
216 return pcie->base + PCIE_CFG_OFFSET_ADDR + where; in mtk_pcie_map_bus()
244 static int mtk_pcie_set_trans_table(struct mtk_gen3_pcie *pcie, in mtk_pcie_set_trans_table() argument
254 dev_err(pcie->dev, "not enough translate table for addr: %#llx, limited to [%d]\n", in mtk_pcie_set_trans_table()
259 table = pcie->base + PCIE_TRANS_TABLE_BASE_REG + in mtk_pcie_set_trans_table()
281 static void mtk_pcie_enable_msi(struct mtk_gen3_pcie *pcie) in mtk_pcie_enable_msi() argument
287 struct mtk_msi_set *msi_set = &pcie->msi_sets[i]; in mtk_pcie_enable_msi()
289 msi_set->base = pcie->base + PCIE_MSI_SET_BASE_REG + in mtk_pcie_enable_msi()
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| D | pci-tegra.c | 362 struct tegra_pcie *pcie; member
375 static inline void afi_writel(struct tegra_pcie *pcie, u32 value, in afi_writel() argument
378 writel(value, pcie->afi + offset); in afi_writel()
381 static inline u32 afi_readl(struct tegra_pcie *pcie, unsigned long offset) in afi_readl() argument
383 return readl(pcie->afi + offset); in afi_readl()
386 static inline void pads_writel(struct tegra_pcie *pcie, u32 value, in pads_writel() argument
389 writel(value, pcie->pads + offset); in pads_writel()
392 static inline u32 pads_readl(struct tegra_pcie *pcie, unsigned long offset) in pads_readl() argument
394 return readl(pcie->pads + offset); in pads_readl()
429 struct tegra_pcie *pcie = bus->sysdata; in tegra_pcie_map_bus() local
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| D | pcie-iproc.c | 401 struct iproc_pcie *pcie = bus->sysdata; in iproc_data() local
402 return pcie; in iproc_data()
410 static inline u16 iproc_pcie_reg_offset(struct iproc_pcie *pcie, in iproc_pcie_reg_offset() argument
413 return pcie->reg_offsets[reg]; in iproc_pcie_reg_offset()
416 static inline u32 iproc_pcie_read_reg(struct iproc_pcie *pcie, in iproc_pcie_read_reg() argument
419 u16 offset = iproc_pcie_reg_offset(pcie, reg); in iproc_pcie_read_reg()
424 return readl(pcie->base + offset); in iproc_pcie_read_reg()
427 static inline void iproc_pcie_write_reg(struct iproc_pcie *pcie, in iproc_pcie_write_reg() argument
430 u16 offset = iproc_pcie_reg_offset(pcie, reg); in iproc_pcie_write_reg()
435 writel(val, pcie->base + offset); in iproc_pcie_write_reg()
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| D | pcie-brcmstb.c | 178 #define IDX_ADDR(pcie) (pcie->reg_offsets[EXT_CFG_INDEX]) argument
179 #define DATA_ADDR(pcie) (pcie->reg_offsets[EXT_CFG_DATA]) argument
180 #define PCIE_RGR1_SW_INIT_1(pcie) (pcie->reg_offsets[RGR1_SW_INIT_1]) argument
218 void (*perst_set)(struct brcm_pcie *pcie, u32 val);
219 void (*bridge_sw_init_set)(struct brcm_pcie *pcie, u32 val);
262 void (*perst_set)(struct brcm_pcie *pcie, u32 val);
263 void (*bridge_sw_init_set)(struct brcm_pcie *pcie, u32 val);
268 static inline bool is_bmips(const struct brcm_pcie *pcie) in is_bmips() argument
270 return pcie->type == BCM7435 || pcie->type == BCM7425; in is_bmips()
347 static int brcm_pcie_set_ssc(struct brcm_pcie *pcie) in brcm_pcie_set_ssc() argument
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| D | pcie-rcar-host.c | 61 struct rcar_pcie pcie; member
109 static u32 rcar_read_conf(struct rcar_pcie *pcie, int where) in rcar_read_conf() argument
112 u32 val = rcar_pci_read_reg(pcie, where & ~3); in rcar_read_conf()
134 static int rcar_pci_write_reg_workaround(struct rcar_pcie *pcie, u32 val, in rcar_pci_write_reg_workaround() argument
141 : "+r"(error):"r"(val), "r"(pcie->base + reg) : "memory"); in rcar_pci_write_reg_workaround()
143 rcar_pci_write_reg(pcie, val, reg); in rcar_pci_write_reg_workaround()
148 static int rcar_pci_read_reg_workaround(struct rcar_pcie *pcie, u32 *val, in rcar_pci_read_reg_workaround() argument
155 : "+r"(error), "=r"(*val) : "r"(pcie->base + reg) : "memory"); in rcar_pci_read_reg_workaround()
160 *val = rcar_pci_read_reg(pcie, reg); in rcar_pci_read_reg_workaround()
170 struct rcar_pcie *pcie = &host->pcie; in rcar_pcie_config_access() local
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| D | pcie-xilinx.c | 113 static inline u32 pcie_read(struct xilinx_pcie *pcie, u32 reg) in pcie_read() argument
115 return readl(pcie->reg_base + reg); in pcie_read()
118 static inline void pcie_write(struct xilinx_pcie *pcie, u32 val, u32 reg) in pcie_write() argument
120 writel(val, pcie->reg_base + reg); in pcie_write()
123 static inline bool xilinx_pcie_link_up(struct xilinx_pcie *pcie) in xilinx_pcie_link_up() argument
125 return (pcie_read(pcie, XILINX_PCIE_REG_PSCR) & in xilinx_pcie_link_up()
133 static void xilinx_pcie_clear_err_interrupts(struct xilinx_pcie *pcie) in xilinx_pcie_clear_err_interrupts() argument
135 struct device *dev = pcie->dev; in xilinx_pcie_clear_err_interrupts()
136 unsigned long val = pcie_read(pcie, XILINX_PCIE_REG_RPEFR); in xilinx_pcie_clear_err_interrupts()
141 pcie_write(pcie, XILINX_PCIE_RPEFR_ALL_MASK, in xilinx_pcie_clear_err_interrupts()
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| D | pcie-mt7621.c | 80 struct mt7621_pcie *pcie; member
104 static inline u32 pcie_read(struct mt7621_pcie *pcie, u32 reg) in pcie_read() argument
106 return readl_relaxed(pcie->base + reg); in pcie_read()
109 static inline void pcie_write(struct mt7621_pcie *pcie, u32 val, u32 reg) in pcie_write() argument
111 writel_relaxed(val, pcie->base + reg); in pcie_write()
128 struct mt7621_pcie *pcie = bus->sysdata; in mt7621_pcie_map_bus() local
132 writel_relaxed(address, pcie->base + RALINK_PCI_CONFIG_ADDR); in mt7621_pcie_map_bus()
134 return pcie->base + RALINK_PCI_CONFIG_DATA + (where & 3); in mt7621_pcie_map_bus()
143 static u32 read_config(struct mt7621_pcie *pcie, unsigned int dev, u32 reg) in read_config() argument
147 pcie_write(pcie, address, RALINK_PCI_CONFIG_ADDR); in read_config()
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| D | pcie-rcar-ep.c | 23 struct rcar_pcie pcie; member
33 static void rcar_pcie_ep_hw_init(struct rcar_pcie *pcie) in rcar_pcie_ep_hw_init() argument
37 rcar_pci_write_reg(pcie, 0, PCIETCTLR); in rcar_pcie_ep_hw_init()
40 rcar_pci_write_reg(pcie, 0, PCIEMSR); in rcar_pcie_ep_hw_init()
43 rcar_rmw32(pcie, REXPCAP(0), 0xff, PCI_CAP_ID_EXP); in rcar_pcie_ep_hw_init()
44 rcar_rmw32(pcie, REXPCAP(PCI_EXP_FLAGS), in rcar_pcie_ep_hw_init()
46 rcar_rmw32(pcie, RCONF(PCI_HEADER_TYPE), 0x7f, in rcar_pcie_ep_hw_init()
50 rcar_rmw32(pcie, REXPCAP(PCI_EXP_SLTCAP), PCI_EXP_SLTCAP_PSN, 0); in rcar_pcie_ep_hw_init()
52 val = rcar_pci_read_reg(pcie, EXPCAP(1)); in rcar_pcie_ep_hw_init()
55 rcar_pci_write_reg(pcie, val, EXPCAP(1)); in rcar_pcie_ep_hw_init()
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| /Linux-v6.1/drivers/pci/controller/mobiveil/ |
| D | pcie-mobiveil-host.c | 53 struct mobiveil_pcie *pcie = bus->sysdata; in mobiveil_pcie_map_bus() local
54 struct mobiveil_root_port *rp = &pcie->rp; in mobiveil_pcie_map_bus()
62 return pcie->csr_axi_slave_base + where; in mobiveil_pcie_map_bus()
74 mobiveil_csr_writel(pcie, value, PAB_AXI_AMAP_PEX_WIN_L(WIN_NUM_0)); in mobiveil_pcie_map_bus()
88 struct mobiveil_pcie *pcie = irq_desc_get_handler_data(desc); in mobiveil_pcie_isr() local
89 struct device *dev = &pcie->pdev->dev; in mobiveil_pcie_isr()
90 struct mobiveil_root_port *rp = &pcie->rp; in mobiveil_pcie_isr()
105 val = mobiveil_csr_readl(pcie, PAB_INTP_AMBA_MISC_STAT); in mobiveil_pcie_isr()
106 mask = mobiveil_csr_readl(pcie, PAB_INTP_AMBA_MISC_ENB); in mobiveil_pcie_isr()
111 shifted_status = mobiveil_csr_readl(pcie, in mobiveil_pcie_isr()
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| D | pcie-mobiveil.c | 28 static void mobiveil_pcie_sel_page(struct mobiveil_pcie *pcie, u8 pg_idx) in mobiveil_pcie_sel_page() argument
32 val = readl(pcie->csr_axi_slave_base + PAB_CTRL); in mobiveil_pcie_sel_page()
36 writel(val, pcie->csr_axi_slave_base + PAB_CTRL); in mobiveil_pcie_sel_page()
39 static void __iomem *mobiveil_pcie_comp_addr(struct mobiveil_pcie *pcie, in mobiveil_pcie_comp_addr() argument
44 mobiveil_pcie_sel_page(pcie, 0); in mobiveil_pcie_comp_addr()
45 return pcie->csr_axi_slave_base + off; in mobiveil_pcie_comp_addr()
48 mobiveil_pcie_sel_page(pcie, OFFSET_TO_PAGE_IDX(off)); in mobiveil_pcie_comp_addr()
49 return pcie->csr_axi_slave_base + OFFSET_TO_PAGE_ADDR(off); in mobiveil_pcie_comp_addr()
99 u32 mobiveil_csr_read(struct mobiveil_pcie *pcie, u32 off, size_t size) in mobiveil_csr_read() argument
105 addr = mobiveil_pcie_comp_addr(pcie, off); in mobiveil_csr_read()
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| D | pcie-layerscape-gen4.c | 45 static inline u32 ls_g4_pcie_pf_readl(struct ls_g4_pcie *pcie, u32 off) in ls_g4_pcie_pf_readl() argument
47 return ioread32(pcie->pci.csr_axi_slave_base + PCIE_PF_OFF + off); in ls_g4_pcie_pf_readl()
50 static inline void ls_g4_pcie_pf_writel(struct ls_g4_pcie *pcie, in ls_g4_pcie_pf_writel() argument
53 iowrite32(val, pcie->pci.csr_axi_slave_base + PCIE_PF_OFF + off); in ls_g4_pcie_pf_writel()
58 struct ls_g4_pcie *pcie = to_ls_g4_pcie(pci); in ls_g4_pcie_link_up() local
61 state = ls_g4_pcie_pf_readl(pcie, PCIE_PF_DBG); in ls_g4_pcie_link_up()
70 static void ls_g4_pcie_disable_interrupt(struct ls_g4_pcie *pcie) in ls_g4_pcie_disable_interrupt() argument
72 struct mobiveil_pcie *mv_pci = &pcie->pci; in ls_g4_pcie_disable_interrupt()
77 static void ls_g4_pcie_enable_interrupt(struct ls_g4_pcie *pcie) in ls_g4_pcie_enable_interrupt() argument
79 struct mobiveil_pcie *mv_pci = &pcie->pci; in ls_g4_pcie_enable_interrupt()
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| /Linux-v6.1/drivers/pci/controller/cadence/ |
| D | pcie-cadence.c | 10 void cdns_pcie_detect_quiet_min_delay_set(struct cdns_pcie *pcie) in cdns_pcie_detect_quiet_min_delay_set() argument
18 ltssm_control_cap = cdns_pcie_readl(pcie, CDNS_PCIE_LTSSM_CONTROL_CAP); in cdns_pcie_detect_quiet_min_delay_set()
23 cdns_pcie_writel(pcie, CDNS_PCIE_LTSSM_CONTROL_CAP, ltssm_control_cap); in cdns_pcie_detect_quiet_min_delay_set()
26 void cdns_pcie_set_outbound_region(struct cdns_pcie *pcie, u8 busnr, u8 fn, in cdns_pcie_set_outbound_region() argument
46 cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_PCI_ADDR0(r), addr0); in cdns_pcie_set_outbound_region()
47 cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_PCI_ADDR1(r), addr1); in cdns_pcie_set_outbound_region()
75 if (pcie->is_rc) { in cdns_pcie_set_outbound_region()
88 cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_DESC0(r), desc0); in cdns_pcie_set_outbound_region()
89 cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_DESC1(r), desc1); in cdns_pcie_set_outbound_region()
92 if (pcie->ops->cpu_addr_fixup) in cdns_pcie_set_outbound_region()
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| D | pcie-cadence-host.c | 31 struct cdns_pcie *pcie = &rc->pcie; in cdns_pci_map_bus() local
44 return pcie->reg_base + (where & 0xfff); in cdns_pci_map_bus()
47 if (!(cdns_pcie_readl(pcie, CDNS_PCIE_LM_BASE) & 0x1)) in cdns_pci_map_bus()
50 cdns_pcie_writel(pcie, CDNS_PCIE_AT_LINKDOWN, 0x0); in cdns_pci_map_bus()
56 cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_PCI_ADDR0(0), addr0); in cdns_pci_map_bus()
69 cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_DESC0(0), desc0); in cdns_pci_map_bus()
80 static int cdns_pcie_host_wait_for_link(struct cdns_pcie *pcie) in cdns_pcie_host_wait_for_link() argument
82 struct device *dev = pcie->dev; in cdns_pcie_host_wait_for_link()
87 if (cdns_pcie_link_up(pcie)) { in cdns_pcie_host_wait_for_link()
97 static int cdns_pcie_retrain(struct cdns_pcie *pcie) in cdns_pcie_retrain() argument
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| D | pcie-cadence-ep.c | 19 static u8 cdns_pcie_get_fn_from_vfn(struct cdns_pcie *pcie, u8 fn, u8 vfn) in cdns_pcie_get_fn_from_vfn() argument
27 first_vf_offset = cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_SRIOV_VF_OFFSET); in cdns_pcie_get_fn_from_vfn()
28 stride = cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_SRIOV_VF_STRIDE); in cdns_pcie_get_fn_from_vfn()
39 struct cdns_pcie *pcie = &ep->pcie; in cdns_pcie_ep_write_header() local
47 cdns_pcie_ep_fn_writew(pcie, fn, reg, hdr->deviceid); in cdns_pcie_ep_write_header()
51 cdns_pcie_ep_fn_writew(pcie, fn, PCI_DEVICE_ID, hdr->deviceid); in cdns_pcie_ep_write_header()
52 cdns_pcie_ep_fn_writeb(pcie, fn, PCI_REVISION_ID, hdr->revid); in cdns_pcie_ep_write_header()
53 cdns_pcie_ep_fn_writeb(pcie, fn, PCI_CLASS_PROG, hdr->progif_code); in cdns_pcie_ep_write_header()
54 cdns_pcie_ep_fn_writew(pcie, fn, PCI_CLASS_DEVICE, in cdns_pcie_ep_write_header()
56 cdns_pcie_ep_fn_writeb(pcie, fn, PCI_CACHE_LINE_SIZE, in cdns_pcie_ep_write_header()
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