| /Linux-v6.1/drivers/gpu/drm/bridge/analogix/ |
| D | analogix_dp_core.c | 262 int lane, lane_count, pll_tries, retval; in analogix_dp_link_start() local
264 lane_count = dp->link_train.lane_count; in analogix_dp_link_start()
269 for (lane = 0; lane < lane_count; lane++) in analogix_dp_link_start()
274 analogix_dp_set_lane_count(dp, dp->link_train.lane_count); in analogix_dp_link_start()
278 buf[1] = dp->link_train.lane_count; in analogix_dp_link_start()
290 for (lane = 0; lane < lane_count; lane++) in analogix_dp_link_start()
316 for (lane = 0; lane < lane_count; lane++) in analogix_dp_link_start()
321 lane_count); in analogix_dp_link_start()
336 static int analogix_dp_clock_recovery_ok(u8 link_status[2], int lane_count) in analogix_dp_clock_recovery_ok() argument
341 for (lane = 0; lane < lane_count; lane++) { in analogix_dp_clock_recovery_ok()
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| /Linux-v6.1/drivers/gpu/drm/amd/display/dc/core/ |
| D | dc_link_dp.c | 75 enum dc_lane_count lane_count; member
110 .lane_count = LANE_COUNT_ONE,
384 uint8_t lane_count) in dp_fixed_vs_pe_set_retimer_lane_settings() argument
399 for (lane = 0; lane < lane_count; lane++) { in dp_fixed_vs_pe_set_retimer_lane_settings()
438 lt_settings->link_settings.lane_count; in dpcd_set_link_settings()
484 lt_settings->link_settings.lane_count, in dpcd_set_link_settings()
494 lt_settings->link_settings.lane_count, in dpcd_set_link_settings()
578 size_in_bytes = lt_settings->link_settings.lane_count * in dpcd_set_lt_pattern_and_lane_settings()
800 for (lane = 1; lane < lt_settings->link_settings.lane_count; lane++) { in maximize_lane_settings()
898 (uint32_t)(link_training_setting->link_settings.lane_count); in dp_get_lane_status_and_lane_adjust()
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| D | dc_link_dpia.c | 302 enum dc_lane_count lane_count = lt_settings->link_settings.lane_count; in dpia_training_cr_non_transparent() local
394 if (dp_is_cr_done(lane_count, dpcd_lane_status)) { in dpia_training_cr_non_transparent()
399 result = dp_get_cr_failure(lane_count, dpcd_lane_status); in dpia_training_cr_non_transparent()
458 enum dc_lane_count lane_count = lt_settings->link_settings.lane_count; in dpia_training_cr_transparent() local
500 if (dp_is_cr_done(lane_count, dpcd_lane_status)) { in dpia_training_cr_transparent()
505 result = dp_get_cr_failure(lane_count, dpcd_lane_status); in dpia_training_cr_transparent()
612 enum dc_lane_count lane_count = lt_settings->link_settings.lane_count; in dpia_training_eq_non_transparent() local
702 if (!dp_is_cr_done(lane_count, dpcd_lane_status)) { in dpia_training_eq_non_transparent()
707 if (dp_is_ch_eq_done(lane_count, dpcd_lane_status) && in dpia_training_eq_non_transparent()
708 dp_is_symbol_locked(link->cur_link_settings.lane_count, dpcd_lane_status) && in dpia_training_eq_non_transparent()
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| /Linux-v6.1/drivers/gpu/drm/msm/dp/ |
| D | dp_panel.h | 90 static inline bool is_lane_count_valid(u32 lane_count) in is_lane_count_valid() argument
92 return (lane_count == 1 || in is_lane_count_valid()
93 lane_count == 2 || in is_lane_count_valid()
94 lane_count == 4); in is_lane_count_valid()
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| D | dp_audio.h | 21 u32 lane_count; member
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| /Linux-v6.1/drivers/gpu/drm/i915/display/ |
| D | intel_dp_link_training.c | 322 lane = min(lane, crtc_state->lane_count - 1); in intel_dp_get_lane_adjust_tx_ffe_preset()
325 for (lane = 0; lane < crtc_state->lane_count; lane++) in intel_dp_get_lane_adjust_tx_ffe_preset()
345 lane = min(lane, crtc_state->lane_count - 1); in intel_dp_get_lane_adjust_vswing_preemph()
350 for (lane = 0; lane < crtc_state->lane_count; lane++) { in intel_dp_get_lane_adjust_vswing_preemph()
421 crtc_state->lane_count, in intel_dp_get_adjust_train()
429 crtc_state->lane_count, in intel_dp_get_adjust_train()
463 memcpy(buf + 1, intel_dp->train_set, crtc_state->lane_count); in intel_dp_set_link_train()
464 len = crtc_state->lane_count + 1; in intel_dp_set_link_train()
541 crtc_state->lane_count, in intel_dp_set_signal_levels()
549 crtc_state->lane_count, in intel_dp_set_signal_levels()
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| D | intel_dpio_phy.c | 590 bxt_ddi_phy_calc_lane_lat_optim_mask(u8 lane_count) in bxt_ddi_phy_calc_lane_lat_optim_mask() argument
592 switch (lane_count) { in bxt_ddi_phy_calc_lane_lat_optim_mask()
600 MISSING_CASE(lane_count); in bxt_ddi_phy_calc_lane_lat_optim_mask()
680 if (crtc_state->lane_count > 2) { in chv_set_phy_signal_level()
693 if (crtc_state->lane_count > 2) { in chv_set_phy_signal_level()
701 for (i = 0; i < crtc_state->lane_count; i++) { in chv_set_phy_signal_level()
709 for (i = 0; i < crtc_state->lane_count; i++) { in chv_set_phy_signal_level()
732 for (i = 0; i < crtc_state->lane_count; i++) { in chv_set_phy_signal_level()
746 if (crtc_state->lane_count > 2) { in chv_set_phy_signal_level()
772 if (crtc_state->lane_count > 2) { in chv_data_lane_soft_reset()
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| D | intel_dp.h | 42 int link_rate, int lane_count);
44 int link_rate, u8 lane_count);
100 static inline unsigned int intel_dp_unused_lane_mask(int lane_count) in intel_dp_unused_lane_mask() argument
102 return ~((1 << lane_count) - 1) & 0xf; in intel_dp_unused_lane_mask()
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| D | vlv_dsi.c | 51 static u16 txbyteclkhs(u16 pixels, int bpp, int lane_count, in txbyteclkhs() argument
55 8 * 100), lane_count); in txbyteclkhs()
59 static u16 pixels_from_txbyteclkhs(u16 clk_hs, int bpp, int lane_count, in pixels_from_txbyteclkhs() argument
62 return DIV_ROUND_UP((clk_hs * lane_count * 8 * 100), in pixels_from_txbyteclkhs()
1108 unsigned int lane_count = intel_dsi->lane_count; in bxt_dsi_get_pipe_config() local
1160 hfp = pixels_from_txbyteclkhs(hfp, bpp, lane_count, in bxt_dsi_get_pipe_config()
1162 hsync = pixels_from_txbyteclkhs(hsync, bpp, lane_count, in bxt_dsi_get_pipe_config()
1164 hbp = pixels_from_txbyteclkhs(hbp, bpp, lane_count, in bxt_dsi_get_pipe_config()
1214 hfp_sw = txbyteclkhs(hfp_sw, bpp, lane_count, in bxt_dsi_get_pipe_config()
1216 hsync_sw = txbyteclkhs(hsync_sw, bpp, lane_count, in bxt_dsi_get_pipe_config()
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| D | intel_combo_phy.c | 274 int lane_count, bool lane_reversal) in intel_combo_phy_power_up_lanes() argument
282 switch (lane_count) { in intel_combo_phy_power_up_lanes()
293 MISSING_CASE(lane_count); in intel_combo_phy_power_up_lanes()
300 switch (lane_count) { in intel_combo_phy_power_up_lanes()
310 MISSING_CASE(lane_count); in intel_combo_phy_power_up_lanes()
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| D | vlv_dsi_pll.c | 48 int lane_count) in dsi_clk_from_pclk() argument
55 dsi_clk_khz = DIV_ROUND_CLOSEST(pclk * bpp, lane_count); in dsi_clk_from_pclk()
168 return DIV_ROUND_CLOSEST(dsi_clock * intel_dsi->lane_count, bpp); in vlv_dsi_pclk()
183 intel_dsi->lane_count); in vlv_dsi_pll_compute()
352 return DIV_ROUND_CLOSEST(dsi_clk * intel_dsi->lane_count, bpp); in bxt_dsi_pclk()
491 intel_dsi->lane_count); in bxt_dsi_pll_compute()
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| D | intel_crtc_state_dump.c | 27 const char *id, unsigned int lane_count, in intel_dump_m_n_config() argument
34 id, lane_count, in intel_dump_m_n_config()
201 pipe_config->lane_count, in intel_crtc_state_dump()
204 pipe_config->lane_count, in intel_crtc_state_dump()
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| D | intel_dp.c | 568 u8 lane_count) in intel_dp_link_params_valid() argument
579 if (lane_count == 0 || in intel_dp_link_params_valid()
580 lane_count > intel_dp_max_lane_count(intel_dp)) in intel_dp_link_params_valid()
588 u8 lane_count) in intel_dp_can_link_train_fallback_for_edp() argument
596 max_rate = intel_dp_max_data_rate(link_rate, lane_count); in intel_dp_can_link_train_fallback_for_edp()
604 int link_rate, u8 lane_count) in intel_dp_get_link_train_fallback_values() argument
632 lane_count)) { in intel_dp_get_link_train_fallback_values()
638 intel_dp->max_link_lane_count = lane_count; in intel_dp_get_link_train_fallback_values()
639 } else if (lane_count > 1) { in intel_dp_get_link_train_fallback_values()
643 lane_count >> 1)) { in intel_dp_get_link_train_fallback_values()
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| D | intel_combo_phy.h | 18 int lane_count, bool lane_reversal);
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| /Linux-v6.1/drivers/gpu/drm/gma500/ |
| D | cdv_intel_dp.c | 261 uint8_t lane_count; member
897 int lane_count, clock; in cdv_intel_dp_mode_fixup() local
910 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) { in cdv_intel_dp_mode_fixup()
912 int link_avail = cdv_intel_dp_max_data_rate(cdv_intel_dp_link_clock(bws[clock]), lane_count); in cdv_intel_dp_mode_fixup()
916 intel_dp->lane_count = lane_count; in cdv_intel_dp_mode_fixup()
920 intel_dp->link_bw, intel_dp->lane_count, in cdv_intel_dp_mode_fixup()
928 intel_dp->lane_count = max_lane_count; in cdv_intel_dp_mode_fixup()
933 intel_dp->link_bw, intel_dp->lane_count, in cdv_intel_dp_mode_fixup()
990 int lane_count = 4, bpp = 24; in cdv_intel_dp_set_m_n() local
1007 lane_count = intel_dp->lane_count; in cdv_intel_dp_set_m_n()
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| /Linux-v6.1/drivers/gpu/drm/bridge/ |
| D | parade-ps8622.c | 55 u32 lane_count; member
185 err = ps8622_set(cl, 0x01, 0x21, 0x80 | ps8622->lane_count); in ps8622_send_config()
491 &ps8622->lane_count)) { in ps8622_probe()
492 ps8622->lane_count = ps8622->max_lane_count; in ps8622_probe()
493 } else if (ps8622->lane_count > ps8622->max_lane_count) { in ps8622_probe()
496 ps8622->lane_count = ps8622->max_lane_count; in ps8622_probe()
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| D | ite-it6505.c | 428 u8 lane_count; member
821 switch (it6505->lane_count) { in it6505_lane_termination_on()
833 switch (it6505->lane_count) { in it6505_lane_termination_on()
865 GENMASK(7, 8 - it6505->lane_count) : in it6505_lane_power_on()
866 GENMASK(3 + it6505->lane_count, 4)) | in it6505_lane_power_on()
1183 it6505->lane_count = MAX_LANE_COUNT; in it6505_variable_config()
1475 it6505->lane_count = link->num_lanes; in it6505_parse_link_capabilities()
1477 it6505->lane_count); in it6505_parse_link_capabilities()
1478 it6505->lane_count = min_t(int, it6505->lane_count, MAX_LANE_COUNT); in it6505_parse_link_capabilities()
1552 (it6505->lane_count - 1) << 1); in it6505_lane_count_setup()
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| /Linux-v6.1/drivers/gpu/drm/mediatek/ |
| D | mtk_dp.c | 73 int lane_count; member
1143 u32 link_rate, int lane_count) in mtk_dp_phy_configure() argument
1150 .lanes = lane_count, in mtk_dp_phy_configure()
1289 mtk_dp->train_info.lane_count = mtk_dp->max_lanes; in mtk_dp_initialize_priv_data()
1311 switch (mtk_dp->train_info.lane_count) { in mtk_dp_sdp_set_down_cnt_init()
1344 switch (mtk_dp->train_info.lane_count) { in mtk_dp_sdp_set_down_cnt_init_in_hblank()
1370 mtk_dp->train_info.lane_count / in mtk_dp_setup_tu()
1651 u8 lane_count, link_rate, train_limit, max_link_rate; in mtk_dp_training() local
1656 lane_count = min_t(u8, mtk_dp->max_lanes, in mtk_dp_training()
1669 ret = mtk_dp_train_setting(mtk_dp, link_rate, lane_count); in mtk_dp_training()
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| /Linux-v6.1/drivers/gpu/drm/amd/display/dc/dcn31/ |
| D | dcn31_dio_link_encoder.c | 479 dpia_control.lanenum = (uint8_t)link_settings->lane_count; in dcn31_link_encoder_enable_dp_output()
526 dpia_control.lanenum = (uint8_t)link_settings->lane_count; in dcn31_link_encoder_enable_dp_mst_output()
662 link_settings->lane_count = MIN(LANE_COUNT_TWO, link_settings->lane_count); in dcn31_link_encoder_get_max_link_cap()
684 link_settings->lane_count = MIN(LANE_COUNT_TWO, link_settings->lane_count); in dcn31_link_encoder_get_max_link_cap()
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| /Linux-v6.1/drivers/gpu/drm/amd/display/dc/dcn201/ |
| D | dcn201_link_encoder.c | 64 if (!value1 && !value2 && link_settings->lane_count > LANE_COUNT_TWO) in dcn201_link_encoder_get_max_link_cap()
65 link_settings->lane_count = LANE_COUNT_TWO; in dcn201_link_encoder_get_max_link_cap()
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| /Linux-v6.1/include/drm/display/ |
| D | drm_dp_helper.h | 37 int lane_count);
39 int lane_count);
62 int lane_count);
64 int lane_count);
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| /Linux-v6.1/drivers/gpu/drm/amd/display/amdgpu_dm/ |
| D | amdgpu_dm_debugfs.c | 203 link->cur_link_settings.lane_count, in dp_link_settings_read()
210 link->verified_link_cap.lane_count, in dp_link_settings_read()
217 link->reported_link_cap.lane_count, in dp_link_settings_read()
224 link->preferred_link_setting.lane_count, in dp_link_settings_read()
322 prefer_link_settings.lane_count = param[0]; in dp_link_settings_write()
533 link_lane_settings.link_settings.lane_count = in dp_phy_settings_write()
534 link->preferred_link_setting.lane_count; in dp_phy_settings_write()
540 link_lane_settings.link_settings.lane_count = in dp_phy_settings_write()
541 link->cur_link_settings.lane_count; in dp_phy_settings_write()
549 for (r = 0; r < link_lane_settings.link_settings.lane_count; r++) { in dp_phy_settings_write()
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| /Linux-v6.1/drivers/media/i2c/ |
| D | ar0521.c | 109 unsigned int lane_count; member
250 unsigned int speed_mod = 4 / sensor->lane_count; /* 1 with 4 DDR lanes */ in ar0521_calc_mode()
767 sensor->lane_count); in ar0521_power_on()
773 ((0x40 << sensor->lane_count) - 0x40) | in ar0521_power_on()
779 4 / sensor->lane_count); in ar0521_power_on()
938 sensor->lane_count = ep.bus.mipi_csi2.num_data_lanes; in ar0521_probe()
939 switch (sensor->lane_count) { in ar0521_probe()
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| /Linux-v6.1/drivers/gpu/drm/amd/display/dc/dce/ |
| D | dce_link_encoder.c | 605 DP_UDI_LANES, link_settings->lane_count - LANE_COUNT_ONE); in configure_encoder()
619 DP_UDI_LANES, link_settings->lane_count - LANE_COUNT_ONE); in dce60_configure_encoder()
1141 cntl.lanes_number = link_settings->lane_count; in dce110_link_encoder_enable_dp_output()
1180 cntl.lanes_number = link_settings->lane_count; in dce110_link_encoder_enable_dp_mst_output()
1220 cntl.lanes_number = link_settings->lane_count; in dce60_link_encoder_enable_dp_output()
1259 cntl.lanes_number = link_settings->lane_count; in dce60_link_encoder_enable_dp_mst_output()
1341 cntl.lanes_number = link_settings->lane_count; in dce110_link_encoder_dp_set_lane_settings()
1346 for (lane = 0; lane < link_settings->lane_count; lane++) { in dce110_link_encoder_dp_set_lane_settings()
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| /Linux-v6.1/drivers/gpu/drm/amd/display/dc/dcn20/ |
| D | dcn20_link_encoder.c | 221 for (i = 0; i < link_settings->lane_count; i++) in update_cfg_data()
281 link_settings->lane_count = MIN(LANE_COUNT_TWO, link_settings->lane_count); in dcn20_link_encoder_get_max_link_cap()
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