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/Linux-v6.1/drivers/gpu/drm/amd/amdgpu/
Damdgpu_rlc.c39 if (adev->gfx.rlc.in_safe_mode) in amdgpu_gfx_rlc_enter_safe_mode()
43 if (!adev->gfx.rlc.funcs->is_rlc_enabled(adev)) in amdgpu_gfx_rlc_enter_safe_mode()
49 adev->gfx.rlc.funcs->set_safe_mode(adev); in amdgpu_gfx_rlc_enter_safe_mode()
50 adev->gfx.rlc.in_safe_mode = true; in amdgpu_gfx_rlc_enter_safe_mode()
63 if (!(adev->gfx.rlc.in_safe_mode)) in amdgpu_gfx_rlc_exit_safe_mode()
67 if (!adev->gfx.rlc.funcs->is_rlc_enabled(adev)) in amdgpu_gfx_rlc_exit_safe_mode()
73 adev->gfx.rlc.funcs->unset_safe_mode(adev); in amdgpu_gfx_rlc_exit_safe_mode()
74 adev->gfx.rlc.in_safe_mode = false; in amdgpu_gfx_rlc_exit_safe_mode()
97 &adev->gfx.rlc.save_restore_obj, in amdgpu_gfx_rlc_init_sr()
98 &adev->gfx.rlc.save_restore_gpu_addr, in amdgpu_gfx_rlc_init_sr()
[all …]
Damdgpu_gfx.c46 bit += mec * adev->gfx.mec.num_pipe_per_mec in amdgpu_gfx_mec_queue_to_bit()
47 * adev->gfx.mec.num_queue_per_pipe; in amdgpu_gfx_mec_queue_to_bit()
48 bit += pipe * adev->gfx.mec.num_queue_per_pipe; in amdgpu_gfx_mec_queue_to_bit()
57 *queue = bit % adev->gfx.mec.num_queue_per_pipe; in amdgpu_queue_mask_bit_to_mec_queue()
58 *pipe = (bit / adev->gfx.mec.num_queue_per_pipe) in amdgpu_queue_mask_bit_to_mec_queue()
59 % adev->gfx.mec.num_pipe_per_mec; in amdgpu_queue_mask_bit_to_mec_queue()
60 *mec = (bit / adev->gfx.mec.num_queue_per_pipe) in amdgpu_queue_mask_bit_to_mec_queue()
61 / adev->gfx.mec.num_pipe_per_mec; in amdgpu_queue_mask_bit_to_mec_queue()
69 adev->gfx.mec.queue_bitmap); in amdgpu_gfx_is_mec_queue_enabled()
77 bit += me * adev->gfx.me.num_pipe_per_me in amdgpu_gfx_me_queue_to_bit()
[all …]
Dgfx_v7_0.c930 err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev); in gfx_v7_0_init_microcode()
933 err = amdgpu_ucode_validate(adev->gfx.pfp_fw); in gfx_v7_0_init_microcode()
938 err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev); in gfx_v7_0_init_microcode()
941 err = amdgpu_ucode_validate(adev->gfx.me_fw); in gfx_v7_0_init_microcode()
946 err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev); in gfx_v7_0_init_microcode()
949 err = amdgpu_ucode_validate(adev->gfx.ce_fw); in gfx_v7_0_init_microcode()
954 err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev); in gfx_v7_0_init_microcode()
957 err = amdgpu_ucode_validate(adev->gfx.mec_fw); in gfx_v7_0_init_microcode()
963 err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev); in gfx_v7_0_init_microcode()
966 err = amdgpu_ucode_validate(adev->gfx.mec2_fw); in gfx_v7_0_init_microcode()
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Dgfx_v6_0.c341 err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev); in gfx_v6_0_init_microcode()
344 err = amdgpu_ucode_validate(adev->gfx.pfp_fw); in gfx_v6_0_init_microcode()
347 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data; in gfx_v6_0_init_microcode()
348 adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); in gfx_v6_0_init_microcode()
349 adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); in gfx_v6_0_init_microcode()
352 err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev); in gfx_v6_0_init_microcode()
355 err = amdgpu_ucode_validate(adev->gfx.me_fw); in gfx_v6_0_init_microcode()
358 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data; in gfx_v6_0_init_microcode()
359 adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version); in gfx_v6_0_init_microcode()
360 adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version); in gfx_v6_0_init_microcode()
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Dgfx_v11_0.c190 if (adev->enable_mes && !adev->gfx.kiq.ring.sched.ready) { in gfx11_kiq_unmap_queues()
258 adev->gfx.kiq.pmf = &gfx_v11_0_kiq_pm4_funcs; in gfx_v11_0_set_kiq_pm4_funcs()
429 release_firmware(adev->gfx.pfp_fw); in gfx_v11_0_free_microcode()
430 adev->gfx.pfp_fw = NULL; in gfx_v11_0_free_microcode()
431 release_firmware(adev->gfx.me_fw); in gfx_v11_0_free_microcode()
432 adev->gfx.me_fw = NULL; in gfx_v11_0_free_microcode()
433 release_firmware(adev->gfx.rlc_fw); in gfx_v11_0_free_microcode()
434 adev->gfx.rlc_fw = NULL; in gfx_v11_0_free_microcode()
435 release_firmware(adev->gfx.mec_fw); in gfx_v11_0_free_microcode()
436 adev->gfx.mec_fw = NULL; in gfx_v11_0_free_microcode()
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Dgfx_v8_0.c927 release_firmware(adev->gfx.pfp_fw); in gfx_v8_0_free_microcode()
928 adev->gfx.pfp_fw = NULL; in gfx_v8_0_free_microcode()
929 release_firmware(adev->gfx.me_fw); in gfx_v8_0_free_microcode()
930 adev->gfx.me_fw = NULL; in gfx_v8_0_free_microcode()
931 release_firmware(adev->gfx.ce_fw); in gfx_v8_0_free_microcode()
932 adev->gfx.ce_fw = NULL; in gfx_v8_0_free_microcode()
933 release_firmware(adev->gfx.rlc_fw); in gfx_v8_0_free_microcode()
934 adev->gfx.rlc_fw = NULL; in gfx_v8_0_free_microcode()
935 release_firmware(adev->gfx.mec_fw); in gfx_v8_0_free_microcode()
936 adev->gfx.mec_fw = NULL; in gfx_v8_0_free_microcode()
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Dgfx_v9_0.c888 adev->gfx.kiq.pmf = &gfx_v9_0_kiq_pm4_funcs; in gfx_v9_0_set_kiq_pm4_funcs()
1078 release_firmware(adev->gfx.pfp_fw); in gfx_v9_0_free_microcode()
1079 adev->gfx.pfp_fw = NULL; in gfx_v9_0_free_microcode()
1080 release_firmware(adev->gfx.me_fw); in gfx_v9_0_free_microcode()
1081 adev->gfx.me_fw = NULL; in gfx_v9_0_free_microcode()
1082 release_firmware(adev->gfx.ce_fw); in gfx_v9_0_free_microcode()
1083 adev->gfx.ce_fw = NULL; in gfx_v9_0_free_microcode()
1084 release_firmware(adev->gfx.rlc_fw); in gfx_v9_0_free_microcode()
1085 adev->gfx.rlc_fw = NULL; in gfx_v9_0_free_microcode()
1086 release_firmware(adev->gfx.mec_fw); in gfx_v9_0_free_microcode()
[all …]
Damdgpu_atomfirmware.c693 adev->gfx.config.max_shader_engines = gfx_info->v24.max_shader_engines; in amdgpu_atomfirmware_get_gfx_info()
694 adev->gfx.config.max_cu_per_sh = gfx_info->v24.max_cu_per_sh; in amdgpu_atomfirmware_get_gfx_info()
695 adev->gfx.config.max_sh_per_se = gfx_info->v24.max_sh_per_se; in amdgpu_atomfirmware_get_gfx_info()
696 adev->gfx.config.max_backends_per_se = gfx_info->v24.max_backends_per_se; in amdgpu_atomfirmware_get_gfx_info()
697 adev->gfx.config.max_texture_channel_caches = gfx_info->v24.max_texture_channel_caches; in amdgpu_atomfirmware_get_gfx_info()
698 adev->gfx.config.max_gprs = le16_to_cpu(gfx_info->v24.gc_num_gprs); in amdgpu_atomfirmware_get_gfx_info()
699 adev->gfx.config.max_gs_threads = gfx_info->v24.gc_num_max_gs_thds; in amdgpu_atomfirmware_get_gfx_info()
700 adev->gfx.config.gs_vgt_table_depth = gfx_info->v24.gc_gs_table_depth; in amdgpu_atomfirmware_get_gfx_info()
701 adev->gfx.config.gs_prim_buffer_depth = in amdgpu_atomfirmware_get_gfx_info()
703 adev->gfx.config.double_offchip_lds_buf = in amdgpu_atomfirmware_get_gfx_info()
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Dgfx_v10_0.c3571 if (adev->enable_mes && !adev->gfx.kiq.ring.sched.ready) { in gfx10_kiq_unmap_queues()
3639 adev->gfx.kiq.pmf = &gfx_v10_0_kiq_pm4_funcs; in gfx_v10_0_set_kiq_pm4_funcs()
3894 release_firmware(adev->gfx.pfp_fw); in gfx_v10_0_free_microcode()
3895 adev->gfx.pfp_fw = NULL; in gfx_v10_0_free_microcode()
3896 release_firmware(adev->gfx.me_fw); in gfx_v10_0_free_microcode()
3897 adev->gfx.me_fw = NULL; in gfx_v10_0_free_microcode()
3898 release_firmware(adev->gfx.ce_fw); in gfx_v10_0_free_microcode()
3899 adev->gfx.ce_fw = NULL; in gfx_v10_0_free_microcode()
3900 release_firmware(adev->gfx.rlc_fw); in gfx_v10_0_free_microcode()
3901 adev->gfx.rlc_fw = NULL; in gfx_v10_0_free_microcode()
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Damdgpu_kms.c223 fw_info->ver = adev->gfx.me_fw_version; in amdgpu_firmware_info()
224 fw_info->feature = adev->gfx.me_feature_version; in amdgpu_firmware_info()
227 fw_info->ver = adev->gfx.pfp_fw_version; in amdgpu_firmware_info()
228 fw_info->feature = adev->gfx.pfp_feature_version; in amdgpu_firmware_info()
231 fw_info->ver = adev->gfx.ce_fw_version; in amdgpu_firmware_info()
232 fw_info->feature = adev->gfx.ce_feature_version; in amdgpu_firmware_info()
235 fw_info->ver = adev->gfx.rlc_fw_version; in amdgpu_firmware_info()
236 fw_info->feature = adev->gfx.rlc_feature_version; in amdgpu_firmware_info()
239 fw_info->ver = adev->gfx.rlc_srlc_fw_version; in amdgpu_firmware_info()
240 fw_info->feature = adev->gfx.rlc_srlc_feature_version; in amdgpu_firmware_info()
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Damdgpu_amdkfd.c151 .num_pipe_per_mec = adev->gfx.mec.num_pipe_per_mec, in amdgpu_amdkfd_device_init()
152 .num_queue_per_pipe = adev->gfx.mec.num_queue_per_pipe, in amdgpu_amdkfd_device_init()
165 adev->gfx.mec.queue_bitmap, in amdgpu_amdkfd_device_init()
172 * adev->gfx.mec.num_pipe_per_mec in amdgpu_amdkfd_device_init()
173 * adev->gfx.mec.num_queue_per_pipe; in amdgpu_amdkfd_device_init()
399 return adev->gfx.pfp_fw_version; in amdgpu_amdkfd_get_fw_version()
402 return adev->gfx.me_fw_version; in amdgpu_amdkfd_get_fw_version()
405 return adev->gfx.ce_fw_version; in amdgpu_amdkfd_get_fw_version()
408 return adev->gfx.mec_fw_version; in amdgpu_amdkfd_get_fw_version()
411 return adev->gfx.mec2_fw_version; in amdgpu_amdkfd_get_fw_version()
[all …]
Damdgpu_ucode.c692 FW_VERSION_ATTR(me_fw_version, 0444, gfx.me_fw_version);
693 FW_VERSION_ATTR(pfp_fw_version, 0444, gfx.pfp_fw_version);
694 FW_VERSION_ATTR(ce_fw_version, 0444, gfx.ce_fw_version);
695 FW_VERSION_ATTR(rlc_fw_version, 0444, gfx.rlc_fw_version);
696 FW_VERSION_ATTR(rlc_srlc_fw_version, 0444, gfx.rlc_srlc_fw_version);
697 FW_VERSION_ATTR(rlc_srlg_fw_version, 0444, gfx.rlc_srlg_fw_version);
698 FW_VERSION_ATTR(rlc_srls_fw_version, 0444, gfx.rlc_srls_fw_version);
699 FW_VERSION_ATTR(mec_fw_version, 0444, gfx.mec_fw_version);
700 FW_VERSION_ATTR(mec2_fw_version, 0444, gfx.mec2_fw_version);
701 FW_VERSION_ATTR(imu_fw_version, 0444, gfx.imu_fw_version);
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Dimu_v11_0.c52 err = request_firmware(&adev->gfx.imu_fw, fw_name, adev->dev); in imu_v11_0_init_microcode()
55 err = amdgpu_ucode_validate(adev->gfx.imu_fw); in imu_v11_0_init_microcode()
58 imu_hdr = (const struct imu_firmware_header_v1_0 *)adev->gfx.imu_fw->data; in imu_v11_0_init_microcode()
59 adev->gfx.imu_fw_version = le32_to_cpu(imu_hdr->header.ucode_version); in imu_v11_0_init_microcode()
65 info->fw = adev->gfx.imu_fw; in imu_v11_0_init_microcode()
70 info->fw = adev->gfx.imu_fw; in imu_v11_0_init_microcode()
80 release_firmware(adev->gfx.imu_fw); in imu_v11_0_init_microcode()
92 if (!adev->gfx.imu_fw) in imu_v11_0_load_microcode()
95 hdr = (const struct imu_firmware_header_v1_0 *)adev->gfx.imu_fw->data; in imu_v11_0_load_microcode()
98 fw_data = (const __le32 *)(adev->gfx.imu_fw->data + in imu_v11_0_load_microcode()
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Damdgpu_amdkfd_gfx_v9.c65 uint32_t mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1; in acquire_queue()
66 uint32_t pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec); in acquire_queue()
74 unsigned int bit = pipe_id * adev->gfx.mec.num_queue_per_pipe + in get_queue_mask()
164 mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1; in kgd_gfx_v9_init_interrupts()
165 pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec); in kgd_gfx_v9_init_interrupts()
303 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; in kgd_gfx_v9_hiq_mqd_load()
312 mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1; in kgd_gfx_v9_hiq_mqd_load()
313 pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec); in kgd_gfx_v9_hiq_mqd_load()
318 spin_lock(&adev->gfx.kiq.ring_lock); in kgd_gfx_v9_hiq_mqd_load()
345 spin_unlock(&adev->gfx.kiq.ring_lock); in kgd_gfx_v9_hiq_mqd_load()
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Damdgpu_debugfs.c130 if ((sh_bank != 0xFFFFFFFF && sh_bank >= adev->gfx.config.max_sh_per_se) || in amdgpu_debugfs_process_reg_op()
131 (se_bank != 0xFFFFFFFF && se_bank >= adev->gfx.config.max_shader_engines)) { in amdgpu_debugfs_process_reg_op()
255 if ((rd->id.grbm.sh != 0xFFFFFFFF && rd->id.grbm.sh >= adev->gfx.config.max_sh_per_se) || in amdgpu_debugfs_regs2_op()
256 (rd->id.grbm.se != 0xFFFFFFFF && rd->id.grbm.se >= adev->gfx.config.max_shader_engines)) { in amdgpu_debugfs_regs2_op()
717 config[no_regs++] = adev->gfx.config.max_shader_engines; in amdgpu_debugfs_gca_config_read()
718 config[no_regs++] = adev->gfx.config.max_tile_pipes; in amdgpu_debugfs_gca_config_read()
719 config[no_regs++] = adev->gfx.config.max_cu_per_sh; in amdgpu_debugfs_gca_config_read()
720 config[no_regs++] = adev->gfx.config.max_sh_per_se; in amdgpu_debugfs_gca_config_read()
721 config[no_regs++] = adev->gfx.config.max_backends_per_se; in amdgpu_debugfs_gca_config_read()
722 config[no_regs++] = adev->gfx.config.max_texture_channel_caches; in amdgpu_debugfs_gca_config_read()
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Damdgpu_discovery.c1309 adev->gfx.config.max_shader_engines = le32_to_cpu(gc_info->v1.gc_num_se); in amdgpu_discovery_get_gfx_info()
1310 adev->gfx.config.max_cu_per_sh = 2 * (le32_to_cpu(gc_info->v1.gc_num_wgp0_per_sa) + in amdgpu_discovery_get_gfx_info()
1312 adev->gfx.config.max_sh_per_se = le32_to_cpu(gc_info->v1.gc_num_sa_per_se); in amdgpu_discovery_get_gfx_info()
1313 adev->gfx.config.max_backends_per_se = le32_to_cpu(gc_info->v1.gc_num_rb_per_se); in amdgpu_discovery_get_gfx_info()
1314 adev->gfx.config.max_texture_channel_caches = le32_to_cpu(gc_info->v1.gc_num_gl2c); in amdgpu_discovery_get_gfx_info()
1315 adev->gfx.config.max_gprs = le32_to_cpu(gc_info->v1.gc_num_gprs); in amdgpu_discovery_get_gfx_info()
1316 adev->gfx.config.max_gs_threads = le32_to_cpu(gc_info->v1.gc_num_max_gs_thds); in amdgpu_discovery_get_gfx_info()
1317 adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gc_info->v1.gc_gs_table_depth); in amdgpu_discovery_get_gfx_info()
1318 adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gc_info->v1.gc_gsprim_buff_depth); in amdgpu_discovery_get_gfx_info()
1319 adev->gfx.config.double_offchip_lds_buf = le32_to_cpu(gc_info->v1.gc_double_offchip_lds_buffer); in amdgpu_discovery_get_gfx_info()
[all …]
Damdgpu_amdkfd_gfx_v11.c57 uint32_t mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1; in acquire_queue()
58 uint32_t pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec); in acquire_queue()
66 unsigned int bit = pipe_id * adev->gfx.mec.num_queue_per_pipe + in get_queue_mask()
109 mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1; in init_interrupts_v11()
110 pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec); in init_interrupts_v11()
180 mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1; in hqd_load_v11()
181 pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec); in hqd_load_v11()
263 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; in hiq_mqd_load_v11()
272 mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1; in hiq_mqd_load_v11()
273 pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec); in hiq_mqd_load_v11()
[all …]
Damdgpu_amdkfd_gfx_v10.c58 uint32_t mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1; in acquire_queue()
59 uint32_t pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec); in acquire_queue()
67 unsigned int bit = pipe_id * adev->gfx.mec.num_queue_per_pipe + in get_queue_mask()
143 mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1; in kgd_init_interrupts()
144 pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec); in kgd_init_interrupts()
291 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; in kgd_hiq_mqd_load()
300 mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1; in kgd_hiq_mqd_load()
301 pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec); in kgd_hiq_mqd_load()
306 spin_lock(&adev->gfx.kiq.ring_lock); in kgd_hiq_mqd_load()
333 spin_unlock(&adev->gfx.kiq.ring_lock); in kgd_hiq_mqd_load()
Damdgpu_amdkfd_gfx_v10_3.c59 uint32_t mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1; in acquire_queue()
60 uint32_t pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec); in acquire_queue()
68 unsigned int bit = pipe_id * adev->gfx.mec.num_queue_per_pipe + in get_queue_mask()
113 mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1; in init_interrupts_v10_3()
114 pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec); in init_interrupts_v10_3()
195 mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1; in hqd_load_v10_3()
196 pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec); in hqd_load_v10_3()
278 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; in hiq_mqd_load_v10_3()
287 mec = (pipe_id / adev->gfx.mec.num_pipe_per_mec) + 1; in hiq_mqd_load_v10_3()
288 pipe = (pipe_id % adev->gfx.mec.num_pipe_per_mec); in hiq_mqd_load_v10_3()
[all …]
Damdgpu_cgs.c173 fw_version = adev->gfx.ce_fw_version; in amdgpu_get_firmware_version()
176 fw_version = adev->gfx.pfp_fw_version; in amdgpu_get_firmware_version()
179 fw_version = adev->gfx.me_fw_version; in amdgpu_get_firmware_version()
182 fw_version = adev->gfx.mec_fw_version; in amdgpu_get_firmware_version()
185 fw_version = adev->gfx.mec_fw_version; in amdgpu_get_firmware_version()
188 fw_version = adev->gfx.mec_fw_version; in amdgpu_get_firmware_version()
191 fw_version = adev->gfx.rlc_fw_version; in amdgpu_get_firmware_version()
Dgfx_v9_4_2.c433 for (se = 0; se < adev->gfx.config.max_shader_engines; se++) { in gfx_v9_4_2_log_wave_assignment()
465 for (se = 0; se < adev->gfx.config.max_shader_engines; se++) in gfx_v9_4_2_wait_for_waves_assigned()
493 int wb_size = adev->gfx.config.max_shader_engines * in gfx_v9_4_2_do_sgprs_init()
501 if (!adev->gfx.compute_ring[0].sched.ready || in gfx_v9_4_2_do_sgprs_init()
502 !adev->gfx.compute_ring[1].sched.ready) in gfx_v9_4_2_do_sgprs_init()
516 &adev->gfx.compute_ring[0], in gfx_v9_4_2_do_sgprs_init()
522 adev->gfx.cu_info.number, in gfx_v9_4_2_do_sgprs_init()
532 adev->gfx.cu_info.number * SIMD_ID_MAX * 2, in gfx_v9_4_2_do_sgprs_init()
541 &adev->gfx.compute_ring[1], in gfx_v9_4_2_do_sgprs_init()
547 adev->gfx.cu_info.number * 2, in gfx_v9_4_2_do_sgprs_init()
[all …]
Damdgpu_virt.c73 struct amdgpu_kiq *kiq = &adev->gfx.kiq; in amdgpu_virt_kiq_reg_write_reg_wait()
541 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_ME, adev->gfx.me_fw_version); in amdgpu_virt_populate_vf2pf_ucode_info()
542 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_PFP, adev->gfx.pfp_fw_version); in amdgpu_virt_populate_vf2pf_ucode_info()
543 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_CE, adev->gfx.ce_fw_version); in amdgpu_virt_populate_vf2pf_ucode_info()
544 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_RLC, adev->gfx.rlc_fw_version); in amdgpu_virt_populate_vf2pf_ucode_info()
545 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_RLC_SRLC, adev->gfx.rlc_srlc_fw_version); in amdgpu_virt_populate_vf2pf_ucode_info()
546 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_RLC_SRLG, adev->gfx.rlc_srlg_fw_version); in amdgpu_virt_populate_vf2pf_ucode_info()
547 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_RLC_SRLS, adev->gfx.rlc_srls_fw_version); in amdgpu_virt_populate_vf2pf_ucode_info()
548 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_MEC, adev->gfx.mec_fw_version); in amdgpu_virt_populate_vf2pf_ucode_info()
549 POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_MEC2, adev->gfx.mec2_fw_version); in amdgpu_virt_populate_vf2pf_ucode_info()
[all …]
/Linux-v6.1/Documentation/devicetree/bindings/gpu/
Daspeed-gfx.txt6 + aspeed,ast2500-gfx
7 + aspeed,ast2400-gfx
26 gfx: display@1e6e6000 {
27 compatible = "aspeed,ast2500-gfx", "syscon";
/Linux-v6.1/Documentation/devicetree/bindings/mfd/
Daspeed-gfx.txt8 - compatible: "aspeed,ast2500-gfx", "syscon"
14 gfx: display@1e6e6000 {
15 compatible = "aspeed,ast2500-gfx", "syscon";
/Linux-v6.1/drivers/soc/qcom/
Drpmhpd.c105 static struct rpmhpd gfx = { variable
198 [SC8280XP_GFX] = &gfx,
218 [SDM845_GFX] = &gfx,
261 [SM6350_GFX] = &gfx,
278 [SM8150_GFX] = &gfx,
298 [SM8250_GFX] = &gfx,
317 [SM8350_GFX] = &gfx,
339 [SM8450_GFX] = &gfx,
360 [SC7180_GFX] = &gfx,
378 [SC7280_GFX] = &gfx,
[all …]

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