73 	struct amdgpu_kiq *kiq = &adev->gfx.kiq;  in amdgpu_virt_kiq_reg_write_reg_wait()
541 	POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_ME,       adev->gfx.me_fw_version);  in amdgpu_virt_populate_vf2pf_ucode_info()
542 	POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_PFP,      adev->gfx.pfp_fw_version);  in amdgpu_virt_populate_vf2pf_ucode_info()
543 	POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_CE,       adev->gfx.ce_fw_version);  in amdgpu_virt_populate_vf2pf_ucode_info()
544 	POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_RLC,      adev->gfx.rlc_fw_version);  in amdgpu_virt_populate_vf2pf_ucode_info()
545 	POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_RLC_SRLC, adev->gfx.rlc_srlc_fw_version);  in amdgpu_virt_populate_vf2pf_ucode_info()
546 	POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_RLC_SRLG, adev->gfx.rlc_srlg_fw_version);  in amdgpu_virt_populate_vf2pf_ucode_info()
547 	POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_RLC_SRLS, adev->gfx.rlc_srls_fw_version);  in amdgpu_virt_populate_vf2pf_ucode_info()
548 	POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_MEC,      adev->gfx.mec_fw_version);  in amdgpu_virt_populate_vf2pf_ucode_info()
549 	POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_MEC2,     adev->gfx.mec2_fw_version);  in amdgpu_virt_populate_vf2pf_ucode_info()
550 	POPULATE_UCODE_INFO(vf2pf_info, AMD_SRIOV_UCODE_ID_IMU,      adev->gfx.imu_fw_version);  in amdgpu_virt_populate_vf2pf_ucode_info()
949 	if (!adev->gfx.rlc.rlcg_reg_access_supported) {  in amdgpu_virt_rlcg_reg_rw()
955 	reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl;  in amdgpu_virt_rlcg_reg_rw()