Searched refs:clk_phase (Results 1 – 6 of 6) sorted by relevance
43 u32 clk_phase[2]; in socfpga_clk_prepare() local45 if (socfpgaclk->clk_phase[0] || socfpgaclk->clk_phase[1]) { in socfpga_clk_prepare()46 for (i = 0; i < ARRAY_SIZE(clk_phase); i++) { in socfpga_clk_prepare()47 switch (socfpgaclk->clk_phase[i]) { in socfpga_clk_prepare()49 clk_phase[i] = 0; in socfpga_clk_prepare()52 clk_phase[i] = 1; in socfpga_clk_prepare()55 clk_phase[i] = 2; in socfpga_clk_prepare()58 clk_phase[i] = 3; in socfpga_clk_prepare()61 clk_phase[i] = 4; in socfpga_clk_prepare()64 clk_phase[i] = 5; in socfpga_clk_prepare()[all …]
117 u32 clk_phase[2]; in socfpga_clk_prepare() local119 if (socfpgaclk->clk_phase[0] || socfpgaclk->clk_phase[1]) { in socfpga_clk_prepare()127 switch (socfpgaclk->clk_phase[i]) { in socfpga_clk_prepare()129 clk_phase[i] = 0; in socfpga_clk_prepare()132 clk_phase[i] = 1; in socfpga_clk_prepare()135 clk_phase[i] = 2; in socfpga_clk_prepare()138 clk_phase[i] = 3; in socfpga_clk_prepare()141 clk_phase[i] = 4; in socfpga_clk_prepare()144 clk_phase[i] = 5; in socfpga_clk_prepare()147 clk_phase[i] = 6; in socfpga_clk_prepare()[all …]
53 u32 clk_phase[2]; member
198 DECLARE_EVENT_CLASS(clk_phase,217 DEFINE_EVENT(clk_phase, clk_set_phase,224 DEFINE_EVENT(clk_phase, clk_set_phase_complete,
1146 int clk_phase = 0; in lm49453_set_dai_fmt() local1173 clk_phase = (1 << 5); in lm49453_set_dai_fmt()1178 clk_phase = (1 << 5); in lm49453_set_dai_fmt()1187 (aif_val | mode | clk_phase)); in lm49453_set_dai_fmt()
1038 u32 clk_phase[2] = {0}; in arasan_dt_read_clk_phase() local1045 ret = of_property_read_variable_u32_array(np, prop, &clk_phase[0], in arasan_dt_read_clk_phase()1055 clk_data->clk_phase_in[timing] = clk_phase[0]; in arasan_dt_read_clk_phase()1056 clk_data->clk_phase_out[timing] = clk_phase[1]; in arasan_dt_read_clk_phase()
