Lines Matching refs:clk_phase
43 u32 clk_phase[2]; in socfpga_clk_prepare() local
45 if (socfpgaclk->clk_phase[0] || socfpgaclk->clk_phase[1]) { in socfpga_clk_prepare()
46 for (i = 0; i < ARRAY_SIZE(clk_phase); i++) { in socfpga_clk_prepare()
47 switch (socfpgaclk->clk_phase[i]) { in socfpga_clk_prepare()
49 clk_phase[i] = 0; in socfpga_clk_prepare()
52 clk_phase[i] = 1; in socfpga_clk_prepare()
55 clk_phase[i] = 2; in socfpga_clk_prepare()
58 clk_phase[i] = 3; in socfpga_clk_prepare()
61 clk_phase[i] = 4; in socfpga_clk_prepare()
64 clk_phase[i] = 5; in socfpga_clk_prepare()
67 clk_phase[i] = 6; in socfpga_clk_prepare()
70 clk_phase[i] = 7; in socfpga_clk_prepare()
73 clk_phase[i] = 0; in socfpga_clk_prepare()
78 hs_timing = SYSMGR_SDMMC_CTRL_SET_AS10(clk_phase[0], clk_phase[1]); in socfpga_clk_prepare()
99 u32 clk_phase[2]; in __socfpga_gate_init() local
139 rc = of_property_read_u32_array(node, "clk-phase", clk_phase, 2); in __socfpga_gate_init()
141 socfpga_clk->clk_phase[0] = clk_phase[0]; in __socfpga_gate_init()
142 socfpga_clk->clk_phase[1] = clk_phase[1]; in __socfpga_gate_init()