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Searched refs:cgu (Results 1 – 25 of 35) sorted by relevance

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/Linux-v6.1/drivers/clk/ingenic/
Dcgu.c30 return &clk->cgu->clock_info[clk->idx]; in to_clk_info()
44 ingenic_cgu_gate_get(struct ingenic_cgu *cgu, in ingenic_cgu_gate_get() argument
47 return !!(readl(cgu->base + info->reg) & BIT(info->bit)) in ingenic_cgu_gate_get()
62 ingenic_cgu_gate_set(struct ingenic_cgu *cgu, in ingenic_cgu_gate_set() argument
65 u32 clkgr = readl(cgu->base + info->reg); in ingenic_cgu_gate_set()
72 writel(clkgr, cgu->base + info->reg); in ingenic_cgu_gate_set()
84 struct ingenic_cgu *cgu = ingenic_clk->cgu; in ingenic_pll_recalc_rate() local
93 ctl = readl(cgu->base + pll_info->reg); in ingenic_pll_recalc_rate()
103 ctl = readl(cgu->base + pll_info->bypass_reg); in ingenic_pll_recalc_rate()
180 static inline int ingenic_pll_check_stable(struct ingenic_cgu *cgu, in ingenic_pll_check_stable() argument
[all …]
DMakefile2 obj-$(CONFIG_INGENIC_CGU_COMMON) += cgu.o pm.o
3 obj-$(CONFIG_INGENIC_CGU_JZ4740) += jz4740-cgu.o
4 obj-$(CONFIG_INGENIC_CGU_JZ4725B) += jz4725b-cgu.o
5 obj-$(CONFIG_INGENIC_CGU_JZ4760) += jz4760-cgu.o
6 obj-$(CONFIG_INGENIC_CGU_JZ4770) += jz4770-cgu.o
7 obj-$(CONFIG_INGENIC_CGU_JZ4780) += jz4780-cgu.o
8 obj-$(CONFIG_INGENIC_CGU_X1000) += x1000-cgu.o
9 obj-$(CONFIG_INGENIC_CGU_X1830) += x1830-cgu.o
Djz4780-cgu.c103 static struct ingenic_cgu *cgu; variable
111 usbpcr1 = readl(cgu->base + CGU_REG_USBPCR1); in jz4780_otg_phy_recalc_rate()
173 spin_lock_irqsave(&cgu->lock, flags); in jz4780_otg_phy_set_rate()
175 usbpcr1 = readl(cgu->base + CGU_REG_USBPCR1); in jz4780_otg_phy_set_rate()
178 writel(usbpcr1, cgu->base + CGU_REG_USBPCR1); in jz4780_otg_phy_set_rate()
180 spin_unlock_irqrestore(&cgu->lock, flags); in jz4780_otg_phy_set_rate()
186 void __iomem *reg_opcr = cgu->base + CGU_REG_OPCR; in jz4780_otg_phy_enable()
187 void __iomem *reg_usbpcr = cgu->base + CGU_REG_USBPCR; in jz4780_otg_phy_enable()
196 void __iomem *reg_opcr = cgu->base + CGU_REG_OPCR; in jz4780_otg_phy_disable()
197 void __iomem *reg_usbpcr = cgu->base + CGU_REG_USBPCR; in jz4780_otg_phy_disable()
[all …]
Dx1000-cgu.c61 static struct ingenic_cgu *cgu; variable
69 usbpcr1 = readl(cgu->base + CGU_REG_USBPCR1); in x1000_otg_phy_recalc_rate()
121 spin_lock_irqsave(&cgu->lock, flags); in x1000_otg_phy_set_rate()
123 usbpcr1 = readl(cgu->base + CGU_REG_USBPCR1); in x1000_otg_phy_set_rate()
126 writel(usbpcr1, cgu->base + CGU_REG_USBPCR1); in x1000_otg_phy_set_rate()
128 spin_unlock_irqrestore(&cgu->lock, flags); in x1000_otg_phy_set_rate()
134 void __iomem *reg_opcr = cgu->base + CGU_REG_OPCR; in x1000_usb_phy_enable()
135 void __iomem *reg_usbpcr = cgu->base + CGU_REG_USBPCR; in x1000_usb_phy_enable()
144 void __iomem *reg_opcr = cgu->base + CGU_REG_OPCR; in x1000_usb_phy_disable()
145 void __iomem *reg_usbpcr = cgu->base + CGU_REG_USBPCR; in x1000_usb_phy_disable()
[all …]
Dx1830-cgu.c55 static struct ingenic_cgu *cgu; variable
59 void __iomem *reg_opcr = cgu->base + CGU_REG_OPCR; in x1830_usb_phy_enable()
60 void __iomem *reg_usbpcr = cgu->base + CGU_REG_USBPCR; in x1830_usb_phy_enable()
69 void __iomem *reg_opcr = cgu->base + CGU_REG_OPCR; in x1830_usb_phy_disable()
70 void __iomem *reg_usbpcr = cgu->base + CGU_REG_USBPCR; in x1830_usb_phy_disable()
78 void __iomem *reg_opcr = cgu->base + CGU_REG_OPCR; in x1830_usb_phy_is_enabled()
79 void __iomem *reg_usbpcr = cgu->base + CGU_REG_USBPCR; in x1830_usb_phy_is_enabled()
453 cgu = ingenic_cgu_new(x1830_cgu_clocks, in x1830_cgu_init()
455 if (!cgu) { in x1830_cgu_init()
460 retval = ingenic_cgu_register_clocks(cgu); in x1830_cgu_init()
[all …]
Djz4770-cgu.c49 static struct ingenic_cgu *cgu; variable
53 void __iomem *reg_opcr = cgu->base + CGU_REG_OPCR; in jz4770_uhc_phy_enable()
54 void __iomem *reg_usbpcr1 = cgu->base + CGU_REG_USBPCR1; in jz4770_uhc_phy_enable()
63 void __iomem *reg_opcr = cgu->base + CGU_REG_OPCR; in jz4770_uhc_phy_disable()
64 void __iomem *reg_usbpcr1 = cgu->base + CGU_REG_USBPCR1; in jz4770_uhc_phy_disable()
72 void __iomem *reg_opcr = cgu->base + CGU_REG_OPCR; in jz4770_uhc_phy_is_enabled()
73 void __iomem *reg_usbpcr1 = cgu->base + CGU_REG_USBPCR1; in jz4770_uhc_phy_is_enabled()
448 cgu = ingenic_cgu_new(jz4770_cgu_clocks, in jz4770_cgu_init()
450 if (!cgu) { in jz4770_cgu_init()
455 retval = ingenic_cgu_register_clocks(cgu); in jz4770_cgu_init()
[all …]
Djz4725b-cgu.c33 static struct ingenic_cgu *cgu; variable
260 cgu = ingenic_cgu_new(jz4725b_cgu_clocks, in jz4725b_cgu_init()
262 if (!cgu) { in jz4725b_cgu_init()
267 retval = ingenic_cgu_register_clocks(cgu); in jz4725b_cgu_init()
271 ingenic_cgu_register_syscore_ops(cgu); in jz4725b_cgu_init()
Djz4740-cgu.c48 static struct ingenic_cgu *cgu; variable
258 cgu = ingenic_cgu_new(jz4740_cgu_clocks, in jz4740_cgu_init()
260 if (!cgu) { in jz4740_cgu_init()
265 retval = ingenic_cgu_register_clocks(cgu); in jz4740_cgu_init()
269 ingenic_cgu_register_syscore_ops(cgu); in jz4740_cgu_init()
Dpm.c39 void ingenic_cgu_register_syscore_ops(struct ingenic_cgu *cgu) in ingenic_cgu_register_syscore_ops() argument
42 ingenic_cgu_base = cgu->base; in ingenic_cgu_register_syscore_ops()
Djz4760-cgu.c427 struct ingenic_cgu *cgu; in jz4760_cgu_init() local
430 cgu = ingenic_cgu_new(jz4760_cgu_clocks, in jz4760_cgu_init()
432 if (!cgu) { in jz4760_cgu_init()
437 retval = ingenic_cgu_register_clocks(cgu); in jz4760_cgu_init()
441 ingenic_cgu_register_syscore_ops(cgu); in jz4760_cgu_init()
Dcgu.h209 struct ingenic_cgu *cgu; member
237 int ingenic_cgu_register_clocks(struct ingenic_cgu *cgu);
/Linux-v6.1/arch/mips/boot/dts/ingenic/
Djz4740.dtsi2 #include <dt-bindings/clock/ingenic,jz4740-cgu.h>
19 clocks = <&cgu JZ4740_CLK_CCLK>;
53 cgu: jz4740-cgu@10000000 { label
54 compatible = "ingenic,jz4740-cgu";
72 clocks = <&cgu JZ4740_CLK_RTC>,
73 <&cgu JZ4740_CLK_EXT>,
74 <&cgu JZ4740_CLK_PCLK>,
75 <&cgu JZ4740_CLK_TCU>;
114 clocks = <&cgu JZ4740_CLK_RTC>;
195 clocks = <&cgu JZ4740_CLK_AIC>,
[all …]
Djz4770.dtsi2 #include <dt-bindings/clock/ingenic,jz4770-cgu.h>
19 clocks = <&cgu JZ4770_CLK_CCLK>;
53 cgu: jz4770-cgu@10000000 { label
54 compatible = "ingenic,jz4770-cgu", "simple-mfd";
69 clocks = <&cgu JZ4770_CLK_OTG_PHY>;
84 clocks = <&cgu JZ4770_CLK_RTC>,
85 <&cgu JZ4770_CLK_EXT>,
86 <&cgu JZ4770_CLK_PCLK>;
241 clocks = <&cgu JZ4770_CLK_AIC>, <&cgu JZ4770_CLK_I2S>,
242 <&cgu JZ4770_CLK_EXT>, <&cgu JZ4770_CLK_PLL0>;
[all …]
Djz4780.dtsi2 #include <dt-bindings/clock/ingenic,jz4780-cgu.h>
20 clocks = <&cgu JZ4780_CLK_CPU>;
29 clocks = <&cgu JZ4780_CLK_CORE1>;
63 cgu: jz4780-cgu@10000000 { label
64 compatible = "ingenic,jz4780-cgu", "simple-mfd";
79 clocks = <&cgu JZ4780_CLK_OTG1>;
105 clocks = <&cgu JZ4780_CLK_RTCLK>,
106 <&cgu JZ4780_CLK_EXCLK>,
107 <&cgu JZ4780_CLK_PCLK>;
156 clocks = <&cgu JZ4780_CLK_RTCLK>;
[all …]
Djz4725b.dtsi2 #include <dt-bindings/clock/ingenic,jz4725b-cgu.h>
19 clocks = <&cgu JZ4725B_CLK_CCLK>;
53 cgu: clock-controller@10000000 { label
54 compatible = "ingenic,jz4725b-cgu";
72 clocks = <&cgu JZ4725B_CLK_RTC>,
73 <&cgu JZ4725B_CLK_EXT>,
74 <&cgu JZ4725B_CLK_PCLK>,
75 <&cgu JZ4725B_CLK_TCU>;
123 clocks = <&cgu JZ4725B_CLK_RTC>;
201 clocks = <&cgu JZ4725B_CLK_AIC>,
[all …]
Dx1000.dtsi3 #include <dt-bindings/clock/ingenic,x1000-cgu.h>
20 clocks = <&cgu X1000_CLK_CPU>;
54 cgu: x1000-cgu@10000000 { label
55 compatible = "ingenic,x1000-cgu", "simple-mfd";
70 clocks = <&cgu X1000_CLK_OTGPHY>;
96 clocks = <&cgu X1000_CLK_OST>;
112 clocks = <&cgu X1000_CLK_RTCLK>,
113 <&cgu X1000_CLK_EXCLK>,
114 <&cgu X1000_CLK_PCLK>,
115 <&cgu X1000_CLK_TCU>;
[all …]
Dx1830.dtsi3 #include <dt-bindings/clock/ingenic,x1830-cgu.h>
20 clocks = <&cgu X1830_CLK_CPU>;
54 cgu: x1830-cgu@10000000 { label
55 compatible = "ingenic,x1830-cgu", "simple-mfd";
70 clocks = <&cgu X1830_CLK_OTGPHY>;
89 clocks = <&cgu X1830_CLK_OST>;
105 clocks = <&cgu X1830_CLK_RTCLK>,
106 <&cgu X1830_CLK_EXCLK>,
107 <&cgu X1830_CLK_PCLK>,
108 <&cgu X1830_CLK_TCU>;
[all …]
Dgcw0.dts440 &cgu {
451 <&cgu JZ4770_CLK_PLL1>,
452 <&cgu JZ4770_CLK_GPU>,
453 <&cgu JZ4770_CLK_RTC>,
454 <&cgu JZ4770_CLK_UHC>,
455 <&cgu JZ4770_CLK_LPCLK_MUX>,
456 <&cgu JZ4770_CLK_MMC0_MUX>,
457 <&cgu JZ4770_CLK_MMC1_MUX>;
460 <&cgu JZ4770_CLK_PLL0>,
461 <&cgu JZ4770_CLK_OSC32K>,
[all …]
Dci20.dts125 &cgu {
130 assigned-clocks = <&cgu JZ4780_CLK_OTGPHY>, <&cgu JZ4780_CLK_RTC>,
131 <&cgu JZ4780_CLK_SSIPLL>, <&cgu JZ4780_CLK_SSI>,
132 <&cgu JZ4780_CLK_HDMI>;
133 assigned-clock-parents = <0>, <&cgu JZ4780_CLK_RTCLK>,
134 <&cgu JZ4780_CLK_MPLL>,
135 <&cgu JZ4780_CLK_SSIPLL>;
Drs90.dts171 clocks = <&cgu JZ4725B_CLK_UDC_PHY>;
296 &cgu {
298 assigned-clocks = <&cgu JZ4725B_CLK_RTC>;
299 assigned-clock-parents = <&cgu JZ4725B_CLK_OSC32K>;
308 assigned-clock-parents = <0>, <0>, <&cgu JZ4725B_CLK_RTC>;
/Linux-v6.1/Documentation/devicetree/bindings/clock/
Dlpc1850-ccu.txt47 clocks = <&cgu BASE_APB3_CLK>, <&cgu BASE_APB1_CLK>,
48 <&cgu BASE_SPIFI_CLK>, <&cgu BASE_CPU_CLK>,
49 <&cgu BASE_PERIPH_CLK>, <&cgu BASE_USB0_CLK>,
50 <&cgu BASE_USB1_CLK>, <&cgu BASE_SPI_CLK>;
61 clocks = <&cgu BASE_AUDIO_CLK>, <&cgu BASE_UART3_CLK>,
62 <&cgu BASE_UART2_CLK>, <&cgu BASE_UART1_CLK>,
63 <&cgu BASE_UART0_CLK>, <&cgu BASE_SSP1_CLK>,
64 <&cgu BASE_SSP0_CLK>, <&cgu BASE_SDIO_CLK>;
/Linux-v6.1/arch/arm/boot/dts/
Dlpc18xx.dtsi16 #include "dt-bindings/clock/lpc18xx-cgu.h"
165 clocks = <&cgu BASE_LCD_CLK>, <&ccu1 CLK_CPU_LCD>;
232 cgu: clock-controller@40050000 { label
233 compatible = "nxp,lpc1850-cgu";
243 clocks = <&cgu BASE_APB3_CLK>, <&cgu BASE_APB1_CLK>,
244 <&cgu BASE_SPIFI_CLK>, <&cgu BASE_CPU_CLK>,
245 <&cgu BASE_PERIPH_CLK>, <&cgu BASE_USB0_CLK>,
246 <&cgu BASE_USB1_CLK>, <&cgu BASE_SPI_CLK>;
257 clocks = <&cgu BASE_AUDIO_CLK>, <&cgu BASE_UART3_CLK>,
258 <&cgu BASE_UART2_CLK>, <&cgu BASE_UART1_CLK>,
[all …]
/Linux-v6.1/drivers/clk/x86/
DMakefile4 obj-$(CONFIG_CLK_LGM_CGU) += clk-cgu.o clk-cgu-pll.o clk-lgm.o
/Linux-v6.1/Documentation/devicetree/bindings/serial/
Dlantiq_asc.txt22 clocks = <&cgu CLK_SSX4>, <&cgu GCLK_UART>;
/Linux-v6.1/Documentation/devicetree/bindings/pinctrl/
Dlantiq,pinctrl-xway.txt57 spi, asc, cgu, jtag, exin, stp, gpt, nmi, pci, ebu
69 spi, asc, cgu, jtag, exin, stp, gpt, nmi, pci, ebu, mdio, gphy
78 spi, asc, cgu, jtag, exin, stp, gpt, mdio, ephy, dfe
89 spi, asc, cgu, jtag, exin, stp, gpt, nmi, pci, ebu, dfe
101 spi, asc, cgu, exin, stp, gpt, nmi, pci, ebu, mdio, dfe
116 spi, usif, cgu, exin, stp, gpt, nmi, pci, ebu, mdio, dfe, gphy
128 spi, usif, cgu, exin, stp, ebu, mdio, dfe, ephy

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