30 	return &clk->cgu->clock_info[clk->idx];  in to_clk_info()
44 ingenic_cgu_gate_get(struct ingenic_cgu *cgu,  in ingenic_cgu_gate_get()  argument
47 	return !!(readl(cgu->base + info->reg) & BIT(info->bit))  in ingenic_cgu_gate_get()
62 ingenic_cgu_gate_set(struct ingenic_cgu *cgu,  in ingenic_cgu_gate_set()  argument
65 	u32 clkgr = readl(cgu->base + info->reg);  in ingenic_cgu_gate_set()
72 	writel(clkgr, cgu->base + info->reg);  in ingenic_cgu_gate_set()
84 	struct ingenic_cgu *cgu = ingenic_clk->cgu;  in ingenic_pll_recalc_rate()  local
93 	ctl = readl(cgu->base + pll_info->reg);  in ingenic_pll_recalc_rate()
103 		ctl = readl(cgu->base + pll_info->bypass_reg);  in ingenic_pll_recalc_rate()
180 static inline int ingenic_pll_check_stable(struct ingenic_cgu *cgu,  in ingenic_pll_check_stable()  argument
185 	return readl_poll_timeout(cgu->base + pll_info->reg, ctl,  in ingenic_pll_check_stable()
195 	struct ingenic_cgu *cgu = ingenic_clk->cgu;  in ingenic_pll_set_rate()  local
209 	spin_lock_irqsave(&cgu->lock, flags);  in ingenic_pll_set_rate()
210 	ctl = readl(cgu->base + pll_info->reg);  in ingenic_pll_set_rate()
221 	writel(ctl, cgu->base + pll_info->reg);  in ingenic_pll_set_rate()
225 		ret = ingenic_pll_check_stable(cgu, pll_info);  in ingenic_pll_set_rate()
227 	spin_unlock_irqrestore(&cgu->lock, flags);  in ingenic_pll_set_rate()
235 	struct ingenic_cgu *cgu = ingenic_clk->cgu;  in ingenic_pll_enable()  local
242 	spin_lock_irqsave(&cgu->lock, flags);  in ingenic_pll_enable()
244 		ctl = readl(cgu->base + pll_info->bypass_reg);  in ingenic_pll_enable()
248 		writel(ctl, cgu->base + pll_info->bypass_reg);  in ingenic_pll_enable()
251 	ctl = readl(cgu->base + pll_info->reg);  in ingenic_pll_enable()
255 	writel(ctl, cgu->base + pll_info->reg);  in ingenic_pll_enable()
257 	ret = ingenic_pll_check_stable(cgu, pll_info);  in ingenic_pll_enable()
258 	spin_unlock_irqrestore(&cgu->lock, flags);  in ingenic_pll_enable()
266 	struct ingenic_cgu *cgu = ingenic_clk->cgu;  in ingenic_pll_disable()  local
272 	spin_lock_irqsave(&cgu->lock, flags);  in ingenic_pll_disable()
273 	ctl = readl(cgu->base + pll_info->reg);  in ingenic_pll_disable()
277 	writel(ctl, cgu->base + pll_info->reg);  in ingenic_pll_disable()
278 	spin_unlock_irqrestore(&cgu->lock, flags);  in ingenic_pll_disable()
284 	struct ingenic_cgu *cgu = ingenic_clk->cgu;  in ingenic_pll_is_enabled()  local
289 	ctl = readl(cgu->base + pll_info->reg);  in ingenic_pll_is_enabled()
312 	struct ingenic_cgu *cgu = ingenic_clk->cgu;  in ingenic_clk_get_parent()  local
317 		reg = readl(cgu->base + clk_info->mux.reg);  in ingenic_clk_get_parent()
338 	struct ingenic_cgu *cgu = ingenic_clk->cgu;  in ingenic_clk_set_parent()  local
366 		spin_lock_irqsave(&cgu->lock, flags);  in ingenic_clk_set_parent()
369 		reg = readl(cgu->base + clk_info->mux.reg);  in ingenic_clk_set_parent()
372 		writel(reg, cgu->base + clk_info->mux.reg);  in ingenic_clk_set_parent()
374 		spin_unlock_irqrestore(&cgu->lock, flags);  in ingenic_clk_set_parent()
386 	struct ingenic_cgu *cgu = ingenic_clk->cgu;  in ingenic_clk_recalc_rate()  local
395 			div_reg = readl(cgu->base + clk_info->div.reg);  in ingenic_clk_recalc_rate()
488 static inline int ingenic_clk_check_stable(struct ingenic_cgu *cgu,  in ingenic_clk_check_stable()  argument
493 	return readl_poll_timeout(cgu->base + clk_info->div.reg, reg,  in ingenic_clk_check_stable()
504 	struct ingenic_cgu *cgu = ingenic_clk->cgu;  in ingenic_clk_set_rate()  local
522 		spin_lock_irqsave(&cgu->lock, flags);  in ingenic_clk_set_rate()
523 		reg = readl(cgu->base + clk_info->div.reg);  in ingenic_clk_set_rate()
539 		writel(reg, cgu->base + clk_info->div.reg);  in ingenic_clk_set_rate()
543 			ret = ingenic_clk_check_stable(cgu, clk_info);  in ingenic_clk_set_rate()
545 		spin_unlock_irqrestore(&cgu->lock, flags);  in ingenic_clk_set_rate()
556 	struct ingenic_cgu *cgu = ingenic_clk->cgu;  in ingenic_clk_enable()  local
561 		spin_lock_irqsave(&cgu->lock, flags);  in ingenic_clk_enable()
562 		ingenic_cgu_gate_set(cgu, &clk_info->gate, false);  in ingenic_clk_enable()
563 		spin_unlock_irqrestore(&cgu->lock, flags);  in ingenic_clk_enable()
576 	struct ingenic_cgu *cgu = ingenic_clk->cgu;  in ingenic_clk_disable()  local
581 		spin_lock_irqsave(&cgu->lock, flags);  in ingenic_clk_disable()
582 		ingenic_cgu_gate_set(cgu, &clk_info->gate, true);  in ingenic_clk_disable()
583 		spin_unlock_irqrestore(&cgu->lock, flags);  in ingenic_clk_disable()
591 	struct ingenic_cgu *cgu = ingenic_clk->cgu;  in ingenic_clk_is_enabled()  local
595 		enabled = !ingenic_cgu_gate_get(cgu, &clk_info->gate);  in ingenic_clk_is_enabled()
617 static int ingenic_register_clock(struct ingenic_cgu *cgu, unsigned idx)  in ingenic_register_clock()  argument
619 	const struct ingenic_cgu_clk_info *clk_info = &cgu->clock_info[idx];  in ingenic_register_clock()
630 		clk = of_clk_get_by_name(cgu->np, clk_info->name);  in ingenic_register_clock()
642 		cgu->clocks.clks[idx] = clk;  in ingenic_register_clock()
659 	ingenic_clk->cgu = cgu;  in ingenic_register_clock()
687 			parent = cgu->clocks.clks[clk_info->parents[i]];  in ingenic_register_clock()
698 		parent = cgu->clocks.clks[clk_info->parents[0]];  in ingenic_register_clock()
753 	cgu->clocks.clks[idx] = clk;  in ingenic_register_clock()
764 	struct ingenic_cgu *cgu;  in ingenic_cgu_new()  local
766 	cgu = kzalloc(sizeof(*cgu), GFP_KERNEL);  in ingenic_cgu_new()
767 	if (!cgu)  in ingenic_cgu_new()
770 	cgu->base = of_iomap(np, 0);  in ingenic_cgu_new()
771 	if (!cgu->base) {  in ingenic_cgu_new()
776 	cgu->np = np;  in ingenic_cgu_new()
777 	cgu->clock_info = clock_info;  in ingenic_cgu_new()
778 	cgu->clocks.clk_num = num_clocks;  in ingenic_cgu_new()
780 	spin_lock_init(&cgu->lock);  in ingenic_cgu_new()
782 	return cgu;  in ingenic_cgu_new()
785 	kfree(cgu);  in ingenic_cgu_new()
790 int ingenic_cgu_register_clocks(struct ingenic_cgu *cgu)  in ingenic_cgu_register_clocks()  argument
795 	cgu->clocks.clks = kcalloc(cgu->clocks.clk_num, sizeof(struct clk *),  in ingenic_cgu_register_clocks()
797 	if (!cgu->clocks.clks) {  in ingenic_cgu_register_clocks()
802 	for (i = 0; i < cgu->clocks.clk_num; i++) {  in ingenic_cgu_register_clocks()
803 		err = ingenic_register_clock(cgu, i);  in ingenic_cgu_register_clocks()
808 	err = of_clk_add_provider(cgu->np, of_clk_src_onecell_get,  in ingenic_cgu_register_clocks()
809 				  &cgu->clocks);  in ingenic_cgu_register_clocks()
816 	for (i = 0; i < cgu->clocks.clk_num; i++) {  in ingenic_cgu_register_clocks()
817 		if (!cgu->clocks.clks[i])  in ingenic_cgu_register_clocks()
819 		if (cgu->clock_info[i].type & CGU_CLK_EXT)  in ingenic_cgu_register_clocks()
820 			clk_put(cgu->clocks.clks[i]);  in ingenic_cgu_register_clocks()
822 			clk_unregister(cgu->clocks.clks[i]);  in ingenic_cgu_register_clocks()
824 	kfree(cgu->clocks.clks);  in ingenic_cgu_register_clocks()