| /Linux-v6.1/drivers/gpu/drm/amd/amdgpu/ |
| D | amdgpu_virt.h | 267 #define amdgpu_sriov_vf(adev) \ macro
277 (amdgpu_sriov_vf((adev)) && !amdgpu_sriov_runtime((adev)))
280 (amdgpu_sriov_vf((adev)) && \
284 (amdgpu_sriov_vf((adev)) && \
288 (amdgpu_sriov_vf((adev)) && \
292 (amdgpu_sriov_vf((adev)) && \
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| D | psp_v11_0_8.c | 63 if (amdgpu_sriov_vf(adev)) { in psp_v11_0_8_ring_stop()
94 if (amdgpu_sriov_vf(adev)) { in psp_v11_0_8_ring_create()
176 if (amdgpu_sriov_vf(adev)) in psp_v11_0_8_ring_get_wptr()
188 if (amdgpu_sriov_vf(adev)) { in psp_v11_0_8_ring_set_wptr()
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| D | psp_v3_1.c | 230 if (amdgpu_sriov_vf(adev)) { in psp_v3_1_ring_create()
292 if (amdgpu_sriov_vf(adev)) in psp_v3_1_ring_stop()
303 if (amdgpu_sriov_vf(adev)) in psp_v3_1_ring_stop()
379 if (amdgpu_sriov_vf(adev)) in psp_v3_1_ring_get_wptr()
390 if (amdgpu_sriov_vf(adev)) { in psp_v3_1_ring_set_wptr()
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| D | athub_v1_0.c | 68 if (amdgpu_sriov_vf(adev)) in athub_v1_0_set_clockgating()
94 if (amdgpu_sriov_vf(adev)) in athub_v1_0_get_clockgating()
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| D | gmc_v11_0.c | 93 if (!amdgpu_sriov_vf(adev)) { in gmc_v11_0_process_interrupt()
121 if (!amdgpu_sriov_vf(adev)) in gmc_v11_0_process_interrupt()
143 if (!amdgpu_sriov_vf(adev)) { in gmc_v11_0_set_irq_funcs()
160 (!amdgpu_sriov_vf(adev))); in gmc_v11_0_use_invalidate_semaphore()
242 !amdgpu_sriov_vf(adev)) { in gmc_v11_0_flush_vm_hub()
281 (amdgpu_sriov_runtime(adev) || !amdgpu_sriov_vf(adev))) { in gmc_v11_0_flush_gpu_tlb()
656 if (amdgpu_sriov_vf(adev)) in gmc_v11_0_vram_gtt_location()
778 if (!amdgpu_sriov_vf(adev)) { in gmc_v11_0_sw_init()
927 if (amdgpu_sriov_vf(adev)) { in gmc_v11_0_hw_fini()
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| D | mmhub_v1_0.c | 113 if (amdgpu_sriov_vf(adev)) in mmhub_v1_0_init_system_aperture_regs()
159 if (amdgpu_sriov_vf(adev)) in mmhub_v1_0_init_cache_regs()
211 if (amdgpu_sriov_vf(adev)) in mmhub_v1_0_disable_identity_aperture()
302 if (amdgpu_sriov_vf(adev)) in mmhub_v1_0_update_power_gating()
313 if (amdgpu_sriov_vf(adev)) { in mmhub_v1_0_gart_enable()
359 if (!amdgpu_sriov_vf(adev)) { in mmhub_v1_0_gart_disable()
378 if (amdgpu_sriov_vf(adev)) in mmhub_v1_0_set_fault_enable_default()
529 if (amdgpu_sriov_vf(adev)) in mmhub_v1_0_set_clockgating()
554 if (amdgpu_sriov_vf(adev)) in mmhub_v1_0_get_clockgating()
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| D | amdgpu_psp.c | 74 if (amdgpu_sriov_vf(adev)) { in psp_check_pmfw_centralized_cstate_management()
184 pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL; in psp_free_shared_bufs()
377 if (amdgpu_sriov_vf(adev)) in psp_sw_init()
448 amdgpu_sriov_vf(adev) ? in psp_sw_init()
640 psp->cmd_buf_mem->resp.status == PSP_ERR_UNKNOWN_COMMAND) && amdgpu_sriov_vf(psp->adev); in psp_cmd_submit_buf()
662 if ((ucode && amdgpu_sriov_vf(psp->adev)) || !timeout) { in psp_cmd_submit_buf()
702 if (amdgpu_sriov_vf(psp->adev)) in psp_prep_tmr_cmd_buf()
764 if (!amdgpu_sriov_vf(psp->adev) && in psp_tmr_init()
776 pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL; in psp_tmr_init()
806 if (amdgpu_sriov_vf(psp->adev) && psp_skip_tmr(psp)) in psp_tmr_load()
[all …]
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| D | amdgpu_device.c | 1208 if (amdgpu_sriov_vf(adev)) in amdgpu_device_resize_fb_bar()
1283 if (amdgpu_sriov_vf(adev)) in amdgpu_device_need_post()
2073 if (amdgpu_sriov_vf(adev)) { in amdgpu_device_ip_early_init()
2148 if (amdgpu_sriov_vf(adev) || sched_policy == KFD_SCHED_POLICY_NO_HWS) in amdgpu_device_ip_early_init()
2150 if (amdgpu_sriov_vf(adev) && adev->asic_type == CHIP_SIENNA_CICHLID) in amdgpu_device_ip_early_init()
2192 if (amdgpu_sriov_vf(adev)) in amdgpu_device_ip_early_init()
2214 (amdgpu_sriov_vf(adev) && (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP)) || in amdgpu_device_ip_hw_init_phase1()
2289 if (!amdgpu_sriov_vf(adev) || adev->asic_type == CHIP_TONGA) in amdgpu_device_fw_loading()
2379 if (amdgpu_sriov_vf(adev)) in amdgpu_device_ip_init()
2400 if (amdgpu_mcbp || amdgpu_sriov_vf(adev)) { in amdgpu_device_ip_init()
[all …]
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| D | psp_v12_0.c | 275 if (amdgpu_sriov_vf(psp->adev)) { in psp_v12_0_ring_create()
327 if (amdgpu_sriov_vf(adev)) in psp_v12_0_ring_stop()
338 if (amdgpu_sriov_vf(adev)) in psp_v12_0_ring_stop()
405 if (amdgpu_sriov_vf(adev)) in psp_v12_0_ring_get_wptr()
417 if (amdgpu_sriov_vf(adev)) { in psp_v12_0_ring_set_wptr()
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| D | nv.c | 188 if (amdgpu_sriov_vf(adev)) { in nv_query_video_codecs()
683 if (!amdgpu_sriov_vf(adev)) { in nv_common_early_init()
779 if (amdgpu_sriov_vf(adev)) in nv_common_early_init()
800 if (amdgpu_sriov_vf(adev)) { in nv_common_early_init()
982 if (amdgpu_sriov_vf(adev)) { in nv_common_early_init()
994 if (amdgpu_sriov_vf(adev)) { in nv_common_late_init()
1008 if (amdgpu_sriov_vf(adev)) in nv_common_sw_init()
1039 if (adev->nbio.funcs->remap_hdp_registers && !amdgpu_sriov_vf(adev)) in nv_common_hw_init()
1091 if (amdgpu_sriov_vf(adev)) in nv_common_set_clockgating_state()
1128 if (amdgpu_sriov_vf(adev)) in nv_common_get_clockgating_state()
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| D | psp_v13_0_4.c | 234 if (amdgpu_sriov_vf(adev)) { in psp_v13_0_4_ring_stop()
265 if (amdgpu_sriov_vf(adev)) { in psp_v13_0_4_ring_create()
347 if (amdgpu_sriov_vf(adev)) in psp_v13_0_4_ring_get_wptr()
359 if (amdgpu_sriov_vf(adev)) { in psp_v13_0_4_ring_set_wptr()
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| D | amdgpu_vf_error.c | 36 if (!amdgpu_sriov_vf(adev)) in amdgpu_vf_error_put()
57 if ((NULL == adev) || (!amdgpu_sriov_vf(adev)) || in amdgpu_vf_error_trans_all()
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| D | sdma_v5_0.c | 205 if (amdgpu_sriov_vf(adev)) in sdma_v5_0_init_golden_registers()
245 if (amdgpu_sriov_vf(adev) && (adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(5, 0, 5))) in sdma_v5_0_init_microcode()
652 if (!amdgpu_sriov_vf(adev)) { in sdma_v5_0_ctx_switch_enable()
666 if (!amdgpu_sriov_vf(adev)) in sdma_v5_0_ctx_switch_enable()
690 if (amdgpu_sriov_vf(adev)) in sdma_v5_0_enable()
723 if (!amdgpu_sriov_vf(adev)) in sdma_v5_0_gfx_resume()
775 if (!amdgpu_sriov_vf(adev)) { /* only bare-metal use register write for wptr */ in sdma_v5_0_gfx_resume()
800 if (amdgpu_sriov_vf(adev)) in sdma_v5_0_gfx_resume()
806 if (!amdgpu_sriov_vf(adev)) { in sdma_v5_0_gfx_resume()
829 if (!amdgpu_sriov_vf(adev)) { in sdma_v5_0_gfx_resume()
[all …]
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| D | mmhub_v2_0.c | 223 if (!amdgpu_sriov_vf(adev)) { in mmhub_v2_0_init_system_aperture_regs()
281 if (amdgpu_sriov_vf(adev)) in mmhub_v2_0_init_cache_regs()
342 if (amdgpu_sriov_vf(adev)) in mmhub_v2_0_disable_identity_aperture()
480 if (amdgpu_sriov_vf(adev)) in mmhub_v2_0_set_fault_enable_default()
651 if (amdgpu_sriov_vf(adev)) in mmhub_v2_0_set_clockgating()
676 if (amdgpu_sriov_vf(adev)) in mmhub_v2_0_get_clockgating()
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| D | mmhub_v3_0.c | 172 if (!amdgpu_sriov_vf(adev)) { in mmhub_v3_0_init_system_aperture_regs()
237 if (amdgpu_sriov_vf(adev)) in mmhub_v3_0_init_cache_regs()
298 if (amdgpu_sriov_vf(adev)) in mmhub_v3_0_disable_identity_aperture()
436 if (amdgpu_sriov_vf(adev)) in mmhub_v3_0_set_fault_enable_default()
619 if (amdgpu_sriov_vf(adev)) in mmhub_v3_0_set_clockgating()
637 if (amdgpu_sriov_vf(adev)) in mmhub_v3_0_get_clockgating()
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| D | mmhub_v3_0_2.c | 170 if (!amdgpu_sriov_vf(adev)) { in mmhub_v3_0_2_init_system_aperture_regs()
230 if (amdgpu_sriov_vf(adev)) in mmhub_v3_0_2_init_cache_regs()
291 if (amdgpu_sriov_vf(adev)) in mmhub_v3_0_2_disable_identity_aperture()
429 if (amdgpu_sriov_vf(adev)) in mmhub_v3_0_2_set_fault_enable_default()
546 if (amdgpu_sriov_vf(adev)) in mmhub_v3_0_2_set_clockgating()
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| D | amdgpu_sdma.c | 75 if (amdgpu_sriov_vf(adev) || vmid == 0 || !amdgpu_mcbp) in amdgpu_sdma_get_csa_mc_addr()
129 if (amdgpu_sriov_vf(adev)) in amdgpu_sdma_process_ras_data_cb()
241 if (amdgpu_sriov_vf(adev)) in amdgpu_sdma_init_microcode()
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| D | gmc_v9_0.c | 596 if (amdgpu_sriov_vf(adev)) in gmc_v9_0_process_interrupt()
686 if (!amdgpu_sriov_vf(adev) && in gmc_v9_0_set_irq_funcs()
727 (!amdgpu_sriov_vf(adev)) && in gmc_v9_0_use_invalidate_semaphore()
791 (amdgpu_sriov_runtime(adev) || !amdgpu_sriov_vf(adev)) && in gmc_v9_0_flush_gpu_tlb()
899 u32 usec_timeout = amdgpu_sriov_vf(adev) ? SRIOV_USEC_TIMEOUT : adev->usec_timeout; in gmc_v9_0_flush_gpu_tlb_pasid()
1375 if (!amdgpu_sriov_vf(adev) && in gmc_v9_0_late_init()
1573 if (amdgpu_sriov_vf(adev)) in gmc_v9_0_sw_init()
1627 if (amdgpu_sriov_vf(adev)) in gmc_v9_0_sw_init()
1664 if (!amdgpu_sriov_vf(adev) && in gmc_v9_0_sw_init()
1742 if (amdgpu_sriov_vf(adev)) in gmc_v9_0_init_golden_registers()
[all …]
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| D | gmc_v10_0.c | 134 if (!amdgpu_sriov_vf(adev)) { in gmc_v10_0_process_interrupt()
165 if (!amdgpu_sriov_vf(adev)) in gmc_v10_0_process_interrupt()
187 if (!amdgpu_sriov_vf(adev)) { in gmc_v10_0_set_irq_funcs()
205 (!amdgpu_sriov_vf(adev))); in gmc_v10_0_use_invalidate_semaphore()
335 (amdgpu_sriov_runtime(adev) || !amdgpu_sriov_vf(adev)) && in gmc_v10_0_flush_gpu_tlb()
422 u32 usec_timeout = amdgpu_sriov_vf(adev) ? SRIOV_USEC_TIMEOUT : adev->usec_timeout; in gmc_v10_0_flush_gpu_tlb_pasid()
967 if (!amdgpu_sriov_vf(adev)) { in gmc_v10_0_sw_init()
1139 if (amdgpu_sriov_vf(adev)) { in gmc_v10_0_hw_fini()
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| D | psp_v13_0.c | 95 if (!amdgpu_sriov_vf(adev)) { in psp_v13_0_init_microcode()
303 if (amdgpu_sriov_vf(adev)) { in psp_v13_0_ring_stop()
334 if (amdgpu_sriov_vf(adev)) { in psp_v13_0_ring_create()
416 if (amdgpu_sriov_vf(adev)) in psp_v13_0_ring_get_wptr()
428 if (amdgpu_sriov_vf(adev)) { in psp_v13_0_ring_set_wptr()
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| D | gfxhub_v1_0.c | 100 if (!amdgpu_sriov_vf(adev) || adev->asic_type <= CHIP_VEGA10) { in gfxhub_v1_0_init_system_aperture_regs()
327 if (!amdgpu_sriov_vf(adev)) in gfxhub_v1_0_gart_enable()
331 if (!amdgpu_sriov_vf(adev)) in gfxhub_v1_0_gart_enable()
350 if (amdgpu_sriov_vf(adev)) in gfxhub_v1_0_gart_disable()
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| D | navi10_ih.c | 123 if (amdgpu_sriov_vf(adev) && amdgpu_sriov_reg_indirect_ih(adev)) { in force_update_wptr_for_self_int()
133 if (amdgpu_sriov_vf(adev) && amdgpu_sriov_reg_indirect_ih(adev)) { in force_update_wptr_for_self_int()
168 if (amdgpu_sriov_vf(adev) && amdgpu_sriov_reg_indirect_ih(adev)) { in navi10_ih_toggle_ring_interrupts()
282 if (amdgpu_sriov_vf(adev) && amdgpu_sriov_reg_indirect_ih(adev)) { in navi10_ih_enable_ring()
496 if (amdgpu_sriov_vf(adev)) in navi10_ih_set_rptr()
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| D | psp_v11_0.c | 396 if (amdgpu_sriov_vf(adev)) in psp_v11_0_ring_stop()
407 if (amdgpu_sriov_vf(adev)) in psp_v11_0_ring_stop()
425 if (amdgpu_sriov_vf(adev)) { in psp_v11_0_ring_create()
698 if (amdgpu_sriov_vf(adev)) in psp_v11_0_ring_get_wptr()
710 if (amdgpu_sriov_vf(adev)) { in psp_v11_0_ring_set_wptr()
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| D | soc15.c | 932 if (!amdgpu_sriov_vf(adev)) { in soc15_common_early_init()
1172 if (amdgpu_sriov_vf(adev)) { in soc15_common_early_init()
1184 if (amdgpu_sriov_vf(adev)) in soc15_common_late_init()
1194 if (amdgpu_sriov_vf(adev)) in soc15_common_sw_init()
1219 if (!amdgpu_sriov_vf(adev)) { in soc15_sdma_doorbell_range_init()
1242 if (adev->nbio.funcs->remap_hdp_registers && !amdgpu_sriov_vf(adev)) in soc15_common_hw_init()
1264 if (amdgpu_sriov_vf(adev)) in soc15_common_hw_fini()
1358 if (amdgpu_sriov_vf(adev)) in soc15_common_set_clockgating_state()
1410 if (amdgpu_sriov_vf(adev)) in soc15_common_get_clockgating_state()
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| D | sdma_v5_2.c | 491 if (!amdgpu_sriov_vf(adev)) { in sdma_v5_2_ctx_switch_enable()
519 if (!amdgpu_sriov_vf(adev)) { in sdma_v5_2_enable()
551 if (!amdgpu_sriov_vf(adev)) in sdma_v5_2_gfx_resume()
601 if (!amdgpu_sriov_vf(adev)) { /* only bare-metal use register write for wptr */ in sdma_v5_2_gfx_resume()
623 if (amdgpu_sriov_vf(adev)) in sdma_v5_2_gfx_resume()
631 if (!amdgpu_sriov_vf(adev)) { in sdma_v5_2_gfx_resume()
675 if (amdgpu_sriov_vf(adev)) { /* bare-metal sequence doesn't need below to lines */ in sdma_v5_2_gfx_resume()
793 if (amdgpu_sriov_vf(adev)) { in sdma_v5_2_start()
1352 if (amdgpu_sriov_vf(adev)) { in sdma_v5_2_hw_fini()
1465 if (!amdgpu_sriov_vf(adev)) { in sdma_v5_2_set_trap_irq_state()
[all …]
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