Searched refs:SEC_CONTROL_REG (Results 1 – 1 of 1) sorted by relevance
55 #define SEC_CONTROL_REG 0x301200 macro425 reg = readl_relaxed(qm->io_base + SEC_CONTROL_REG); in sec_set_endian()434 writel_relaxed(reg, qm->io_base + SEC_CONTROL_REG); in sec_set_endian()518 val = readl_relaxed(qm->io_base + SEC_CONTROL_REG); in sec_enable_clock_gate()520 writel_relaxed(val, qm->io_base + SEC_CONTROL_REG); in sec_enable_clock_gate()536 val = readl_relaxed(qm->io_base + SEC_CONTROL_REG); in sec_disable_clock_gate()538 writel_relaxed(val, qm->io_base + SEC_CONTROL_REG); in sec_disable_clock_gate()559 reg = readl_relaxed(qm->io_base + SEC_CONTROL_REG); in sec_engine_init()561 writel_relaxed(reg, qm->io_base + SEC_CONTROL_REG); in sec_engine_init()636 val1 = readl(qm->io_base + SEC_CONTROL_REG); in sec_master_ooo_ctrl()[all …]
