Lines Matching refs:SEC_CONTROL_REG
55 #define SEC_CONTROL_REG 0x301200 macro
425 reg = readl_relaxed(qm->io_base + SEC_CONTROL_REG); in sec_set_endian()
434 writel_relaxed(reg, qm->io_base + SEC_CONTROL_REG); in sec_set_endian()
518 val = readl_relaxed(qm->io_base + SEC_CONTROL_REG); in sec_enable_clock_gate()
520 writel_relaxed(val, qm->io_base + SEC_CONTROL_REG); in sec_enable_clock_gate()
536 val = readl_relaxed(qm->io_base + SEC_CONTROL_REG); in sec_disable_clock_gate()
538 writel_relaxed(val, qm->io_base + SEC_CONTROL_REG); in sec_disable_clock_gate()
559 reg = readl_relaxed(qm->io_base + SEC_CONTROL_REG); in sec_engine_init()
561 writel_relaxed(reg, qm->io_base + SEC_CONTROL_REG); in sec_engine_init()
636 val1 = readl(qm->io_base + SEC_CONTROL_REG); in sec_master_ooo_ctrl()
649 writel(val1, qm->io_base + SEC_CONTROL_REG); in sec_master_ooo_ctrl()
1019 val = readl(qm->io_base + SEC_CONTROL_REG); in sec_open_axi_master_ooo()
1020 writel(val & SEC_AXI_SHUTDOWN_DISABLE, qm->io_base + SEC_CONTROL_REG); in sec_open_axi_master_ooo()
1021 writel(val | SEC_AXI_SHUTDOWN_ENABLE, qm->io_base + SEC_CONTROL_REG); in sec_open_axi_master_ooo()