Searched refs:S3C_HSUDC_REG (Results 1 – 1 of 1) sorted by relevance
33 #define S3C_HSUDC_REG(x) (x) macro36 #define S3C_IR S3C_HSUDC_REG(0x00) /* Index Register */37 #define S3C_EIR S3C_HSUDC_REG(0x04) /* EP Intr Status */39 #define S3C_EIER S3C_HSUDC_REG(0x08) /* EP Intr Enable */40 #define S3C_FAR S3C_HSUDC_REG(0x0c) /* Gadget Address */41 #define S3C_FNR S3C_HSUDC_REG(0x10) /* Frame Number */42 #define S3C_EDR S3C_HSUDC_REG(0x14) /* EP Direction */43 #define S3C_TR S3C_HSUDC_REG(0x18) /* Test Register */44 #define S3C_SSR S3C_HSUDC_REG(0x1c) /* System Status */53 #define S3C_SCR S3C_HSUDC_REG(0x20) /* System Control */[all …]
