Lines Matching refs:S3C_HSUDC_REG
33 #define S3C_HSUDC_REG(x) (x) macro
36 #define S3C_IR S3C_HSUDC_REG(0x00) /* Index Register */
37 #define S3C_EIR S3C_HSUDC_REG(0x04) /* EP Intr Status */
39 #define S3C_EIER S3C_HSUDC_REG(0x08) /* EP Intr Enable */
40 #define S3C_FAR S3C_HSUDC_REG(0x0c) /* Gadget Address */
41 #define S3C_FNR S3C_HSUDC_REG(0x10) /* Frame Number */
42 #define S3C_EDR S3C_HSUDC_REG(0x14) /* EP Direction */
43 #define S3C_TR S3C_HSUDC_REG(0x18) /* Test Register */
44 #define S3C_SSR S3C_HSUDC_REG(0x1c) /* System Status */
53 #define S3C_SCR S3C_HSUDC_REG(0x20) /* System Control */
58 #define S3C_EP0SR S3C_HSUDC_REG(0x24) /* EP0 Status */
63 #define S3C_EP0CR S3C_HSUDC_REG(0x28) /* EP0 Control */
64 #define S3C_BR(_x) S3C_HSUDC_REG(0x60 + (_x * 4))
67 #define S3C_ESR S3C_HSUDC_REG(0x2c) /* EPn Status */
75 #define S3C_ECR S3C_HSUDC_REG(0x30) /* EPn Control */
80 #define S3C_BRCR S3C_HSUDC_REG(0x34) /* Read Count */
81 #define S3C_BWCR S3C_HSUDC_REG(0x38) /* Write Count */
82 #define S3C_MPR S3C_HSUDC_REG(0x3c) /* Max Pkt Size */