| /Linux-v6.1/include/dt-bindings/clock/ |
| D | mt7986-clk.h | 53 #define CLK_TOP_UART_SEL 30 macro
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| D | mt8135-clk.h | 88 #define CLK_TOP_UART_SEL 77 macro
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| D | mt7629-clk.h | 91 #define CLK_TOP_UART_SEL 81 macro
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| D | mt7622-clk.h | 76 #define CLK_TOP_UART_SEL 64 macro
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| D | mediatek,mt6795-clk.h | 99 #define CLK_TOP_UART_SEL 88 macro
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| D | mt6765-clk.h | 141 #define CLK_TOP_UART_SEL 106 macro
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| D | mt8173-clk.h | 101 #define CLK_TOP_UART_SEL 91 macro
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| D | mediatek,mt8365-clk.h | 79 #define CLK_TOP_UART_SEL 69 macro
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| D | mt2712-clk.h | 138 #define CLK_TOP_UART_SEL 107 macro
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| D | mt2701-clk.h | 98 #define CLK_TOP_UART_SEL 87 macro
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| D | mt8192-clk.h | 33 #define CLK_TOP_UART_SEL 21 macro
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| /Linux-v6.1/arch/arm/boot/dts/ |
| D | mt7629.dtsi | 216 clocks = <&topckgen CLK_TOP_UART_SEL>,
227 clocks = <&topckgen CLK_TOP_UART_SEL>,
238 clocks = <&topckgen CLK_TOP_UART_SEL>,
|
| /Linux-v6.1/arch/arm64/boot/dts/mediatek/ |
| D | mt7986a.dtsi | 188 assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
191 <&topckgen CLK_TOP_UART_SEL>;
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| D | mt7622.dtsi | 396 clocks = <&topckgen CLK_TOP_UART_SEL>,
407 clocks = <&topckgen CLK_TOP_UART_SEL>,
418 clocks = <&topckgen CLK_TOP_UART_SEL>,
429 clocks = <&topckgen CLK_TOP_UART_SEL>,
606 clocks = <&topckgen CLK_TOP_UART_SEL>,
|
| /Linux-v6.1/drivers/clk/mediatek/ |
| D | clk-mt7986-topckgen.c | 186 MUX_GATE_CLR_SET_UPD(CLK_TOP_UART_SEL, "uart_sel", uart_parents, 0x010,
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| D | clk-mt6795-topckgen.c | 466 TOP_MUX_GATE(CLK_TOP_UART_SEL, "uart_sel", uart_parents, 0x60, 8, 1, 15, 0),
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| D | clk-mt8135.c | 374 MUX_GATE(CLK_TOP_UART_SEL, "uart_sel", uart_parents, 0x0150, 24, 2, 31),
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| D | clk-mt7629.c | 506 MUX_GATE(CLK_TOP_UART_SEL, "uart_sel", uart_parents,
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| D | clk-mt7622.c | 536 MUX_GATE(CLK_TOP_UART_SEL, "uart_sel", uart_parents,
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| D | clk-mt2701.c | 506 MUX_GATE(CLK_TOP_UART_SEL, "uart_sel", uart_parents,
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| D | clk-mt2712.c | 757 MUX_GATE(CLK_TOP_UART_SEL, "uart_sel",
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| D | clk-mt6765.c | 400 MUX_GATE_CLR_SET_UPD(CLK_TOP_UART_SEL, "uart_sel", uart_parents,
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| D | clk-mt8173.c | 554 MUX_GATE(CLK_TOP_UART_SEL, "uart_sel", uart_parents, 0x0060, 8, 1, 15),
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| D | clk-mt8192.c | 604 MUX_GATE_CLR_SET_UPD(CLK_TOP_UART_SEL, "uart_sel",
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| D | clk-mt8365.c | 437 MUX_GATE_CLR_SET_UPD(CLK_TOP_UART_SEL, "uart_sel", uart_parents, 0x060,
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