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Searched refs:CLK_TOP_MSDC30_2_SEL (Results 1 – 12 of 12) sorted by relevance

/Linux-v6.1/include/dt-bindings/clock/
Dmt8135-clk.h82 #define CLK_TOP_MSDC30_2_SEL 71 macro
Dmediatek,mt6795-clk.h106 #define CLK_TOP_MSDC30_2_SEL 95 macro
Dmt8173-clk.h108 #define CLK_TOP_MSDC30_2_SEL 98 macro
Dmt2712-clk.h145 #define CLK_TOP_MSDC30_2_SEL 114 macro
Dmt2701-clk.h101 #define CLK_TOP_MSDC30_2_SEL 90 macro
Dmt8192-clk.h38 #define CLK_TOP_MSDC30_2_SEL 26 macro
/Linux-v6.1/drivers/clk/mediatek/
Dclk-mt6795-topckgen.c476 TOP_MUX_GATE(CLK_TOP_MSDC30_2_SEL, "msdc30_2_sel", msdc30_2_parents, 0x80, 0, 3, 7, 0),
Dclk-mt8135.c366 MUX_GATE(CLK_TOP_MSDC30_2_SEL, "msdc30_2_sel", msdc30_parents, 0x0148, 8, 3, 15),
Dclk-mt2701.c518 MUX_GATE(CLK_TOP_MSDC30_2_SEL, "msdc30_2_sel", msdc30_parents,
Dclk-mt2712.c773 MUX_GATE(CLK_TOP_MSDC30_2_SEL, "msdc30_2_sel",
Dclk-mt8173.c563 MUX_GATE(CLK_TOP_MSDC30_2_SEL, "msdc30_2_sel", msdc30_2_parents, 0x0080, 0, 3, 7),
Dclk-mt8192.c615 MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC30_2_SEL, "msdc30_2_sel",