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Searched refs:CLK_TOP_MSDC30_1_SEL (Results 1 – 24 of 24) sorted by relevance

/Linux-v6.1/include/dt-bindings/clock/
Dmt8135-clk.h81 #define CLK_TOP_MSDC30_1_SEL 70 macro
Dmt7629-clk.h96 #define CLK_TOP_MSDC30_1_SEL 86 macro
Dmt7622-clk.h81 #define CLK_TOP_MSDC30_1_SEL 69 macro
Dmediatek,mt6795-clk.h105 #define CLK_TOP_MSDC30_1_SEL 94 macro
Dmt6765-clk.h145 #define CLK_TOP_MSDC30_1_SEL 110 macro
Dmt8173-clk.h107 #define CLK_TOP_MSDC30_1_SEL 97 macro
Dmediatek,mt8365-clk.h85 #define CLK_TOP_MSDC30_1_SEL 75 macro
Dmt2712-clk.h144 #define CLK_TOP_MSDC30_1_SEL 113 macro
Dmt2701-clk.h102 #define CLK_TOP_MSDC30_1_SEL 91 macro
Dmt8192-clk.h37 #define CLK_TOP_MSDC30_1_SEL 25 macro
/Linux-v6.1/drivers/clk/mediatek/
Dclk-mt6795-topckgen.c474 TOP_MUX_GATE(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel", msdc30_1_parents, 0x70, 24, 3, 31, 0),
Dclk-mt8135.c365 MUX_GATE(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel", msdc30_parents, 0x0148, 0, 3, 7),
Dclk-mt7629.c517 MUX_GATE(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel", msdc30_1_parents,
Dclk-mt7622.c548 MUX_GATE(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel", msdc30_0_parents,
Dclk-mt2701.c516 MUX_GATE(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel", msdc30_parents,
Dclk-mt2712.c770 MUX_GATE(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel",
Dclk-mt6765.c413 MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel",
Dclk-mt8173.c561 MUX_GATE(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel", msdc30_1_parents, 0x0070, 24, 3, 31),
Dclk-mt8192.c613 MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel",
Dclk-mt8365.c454 MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel",
/Linux-v6.1/arch/arm64/boot/dts/mediatek/
Dmt7622-rfb1.dts215 assigned-clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>;
Dmt7622-bananapi-bpi-r64.dts242 assigned-clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>;
Dmt8192.dtsi1189 clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>,
/Linux-v6.1/arch/arm/boot/dts/
Dmt7623.dtsi733 <&topckgen CLK_TOP_MSDC30_1_SEL>;