Searched refs:CLK_TOP_MM_SEL (Results 1 – 17 of 17) sorted by relevance
| /Linux-v6.1/include/dt-bindings/clock/ |
| D | mediatek,mt6795-clk.h | 93 #define CLK_TOP_MM_SEL 82 macro
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| D | mt6765-clk.h | 133 #define CLK_TOP_MM_SEL 98 macro
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| D | mt8173-clk.h | 95 #define CLK_TOP_MM_SEL 85 macro
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| D | mediatek,mt8365-clk.h | 73 #define CLK_TOP_MM_SEL 63 macro
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| D | mt2712-clk.h | 132 #define CLK_TOP_MM_SEL 101 macro
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| D | mt2701-clk.h | 87 #define CLK_TOP_MM_SEL 76 macro
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| /Linux-v6.1/arch/arm64/boot/dts/mediatek/ |
| D | mt8173.dtsi | 460 clocks = <&topckgen CLK_TOP_MM_SEL>;
466 clocks = <&topckgen CLK_TOP_MM_SEL>,
473 clocks = <&topckgen CLK_TOP_MM_SEL>;
479 clocks = <&topckgen CLK_TOP_MM_SEL>;
486 clocks = <&topckgen CLK_TOP_MM_SEL>,
992 assigned-clocks = <&topckgen CLK_TOP_MM_SEL>;
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| D | mt2712e.dtsi | 285 clocks = <&topckgen CLK_TOP_MM_SEL>,
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| /Linux-v6.1/Documentation/devicetree/bindings/soc/mediatek/ |
| D | scpsys.txt | 67 <&topckgen CLK_TOP_MM_SEL>;
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| /Linux-v6.1/drivers/clk/mediatek/ |
| D | clk-mt6795-topckgen.c | 458 TOP_MUX_GATE(CLK_TOP_MM_SEL, "mm_sel", mm_parents, 0x40, 24, 3, 31, 0),
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| D | clk-mt2701.c | 495 MUX_GATE(CLK_TOP_MM_SEL, "mm_sel", mm_parents,
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| D | clk-mt2712.c | 743 MUX_GATE(CLK_TOP_MM_SEL, "mm_sel",
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| D | clk-mt6765.c | 374 MUX_GATE_CLR_SET_UPD(CLK_TOP_MM_SEL, "mm_sel", mm_parents, CLK_CFG_0,
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| D | clk-mt8173.c | 546 MUX_GATE(CLK_TOP_MM_SEL, "mm_sel", mm_parents, 0x0040, 24, 4, 31),
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| D | clk-mt8365.c | 423 MUX_GATE_CLR_SET_UPD(CLK_TOP_MM_SEL, "mm_sel", mm_parents, 0x040, 0x044,
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| /Linux-v6.1/arch/arm/boot/dts/ |
| D | mt2701.dtsi | 156 clocks = <&topckgen CLK_TOP_MM_SEL>,
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| D | mt7623.dtsi | 278 clocks = <&topckgen CLK_TOP_MM_SEL>,
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