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Searched refs:CLK_TOP_MEM_SEL (Results 1 – 18 of 18) sorted by relevance

/Linux-v6.1/include/dt-bindings/clock/
Dmt8135-clk.h89 #define CLK_TOP_MEM_SEL 78 macro
Dmt7629-clk.h84 #define CLK_TOP_MEM_SEL 74 macro
Dmt7622-clk.h69 #define CLK_TOP_MEM_SEL 57 macro
Dmediatek,mt6795-clk.h91 #define CLK_TOP_MEM_SEL 80 macro
Dmt6765-clk.h132 #define CLK_TOP_MEM_SEL 97 macro
Dmt8173-clk.h93 #define CLK_TOP_MEM_SEL 83 macro
Dmediatek,mt8365-clk.h72 #define CLK_TOP_MEM_SEL 62 macro
Dmt2712-clk.h131 #define CLK_TOP_MEM_SEL 100 macro
Dmt2701-clk.h89 #define CLK_TOP_MEM_SEL 78 macro
/Linux-v6.1/drivers/clk/mediatek/
Dclk-mt7629.c490 MUX_GATE(CLK_TOP_MEM_SEL, "mem_sel", mem_parents,
595 clk_prepare_enable(clk_data->hws[CLK_TOP_MEM_SEL]->clk); in mtk_topckgen_init()
Dclk-mt7622.c518 MUX_GATE(CLK_TOP_MEM_SEL, "mem_sel", mem_parents,
659 clk_prepare_enable(clk_data->hws[CLK_TOP_MEM_SEL]->clk); in mtk_topckgen_init()
Dclk-mt6795-topckgen.c454 TOP_MUX_GATE_NOSR(CLK_TOP_MEM_SEL, "mem_sel", mem_parents,
Dclk-mt8173.c544 MUX(CLK_TOP_MEM_SEL, "mem_sel", mem_parents, 0x0040, 8, 1),
850 clk_prepare_enable(mt8173_top_clk_data->hws[CLK_TOP_MEM_SEL]->clk); in mtk_clk_enable_critical()
Dclk-mt8135.c376 MUX_GATE(CLK_TOP_MEM_SEL, "mem_sel", mem_parents, 0x0158, 0, 2, 7),
Dclk-mt2701.c491 MUX_GATE_FLAGS(CLK_TOP_MEM_SEL, "mem_sel", mem_parents,
Dclk-mt2712.c741 MUX_GATE_FLAGS(CLK_TOP_MEM_SEL, "mem_sel", mem_parents, 0x040, 8, 1,
Dclk-mt6765.c371 MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MEM_SEL, "mem_sel", mem_parents,
Dclk-mt8365.c421 MUX_GATE_CLR_SET_UPD(CLK_TOP_MEM_SEL, "mem_sel", mem_parents, 0x040,