Searched refs:CLK_TOP_APLL2_DIV1 (Results 1 – 4 of 4) sorted by relevance
| /Linux-v6.1/include/dt-bindings/clock/ |
| D | mediatek,mt6795-clk.h | 133 #define CLK_TOP_APLL2_DIV1 122 macro
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| D | mt8173-clk.h | 138 #define CLK_TOP_APLL2_DIV1 128 macro
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| /Linux-v6.1/drivers/clk/mediatek/ |
| D | clk-mt6795-topckgen.c | 519 DIV_GATE(CLK_TOP_APLL2_DIV1, "apll2_div1", "aud_2_sel", 0x12c, 17, 0x128, 8, 0),
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| D | clk-mt8173.c | 604 DIV_GATE(CLK_TOP_APLL2_DIV1, "apll2_div1", "aud_2_sel", 0x12c, 17, 0x128, 8, 0),
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