Searched refs:CLK_TOP_APLL1_DIV1 (Results 1 – 4 of 4) sorted by relevance
| /Linux-v6.1/include/dt-bindings/clock/ |
| D | mediatek,mt6795-clk.h | 127 #define CLK_TOP_APLL1_DIV1 116 macro
|
| D | mt8173-clk.h | 132 #define CLK_TOP_APLL1_DIV1 122 macro
|
| /Linux-v6.1/drivers/clk/mediatek/ |
| D | clk-mt6795-topckgen.c | 512 DIV_GATE(CLK_TOP_APLL1_DIV1, "apll1_div1", "aud_1_sel", 0x12c, 9, 0x124, 8, 0),
|
| D | clk-mt8173.c | 597 DIV_GATE(CLK_TOP_APLL1_DIV1, "apll1_div1", "aud_1_sel", 0x12c, 9, 0x124, 8, 0),
|
