Searched refs:CLK_TOP_APLL1_DIV0 (Results 1 – 5 of 5) sorted by relevance
| /Linux-v6.1/include/dt-bindings/clock/ |
| D | mediatek,mt6795-clk.h | 126 #define CLK_TOP_APLL1_DIV0 115 macro
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| D | mt8173-clk.h | 131 #define CLK_TOP_APLL1_DIV0 121 macro
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| /Linux-v6.1/drivers/clk/mediatek/ |
| D | clk-mt6795-topckgen.c | 511 DIV_GATE(CLK_TOP_APLL1_DIV0, "apll1_div0", "aud_1_sel", 0x12c, 8, 0x120, 4, 24),
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| D | clk-mt8173.c | 596 DIV_GATE(CLK_TOP_APLL1_DIV0, "apll1_div0", "aud_1_sel", 0x12c, 8, 0x120, 4, 24),
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| /Linux-v6.1/arch/arm64/boot/dts/mediatek/ |
| D | mt8173.dtsi | 861 <&topckgen CLK_TOP_APLL1_DIV0>,
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