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Searched refs:writel_relaxed (Results 1 – 25 of 613) sorted by relevance

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/Linux-v5.4/drivers/phy/qualcomm/
Dphy-qcom-apq8064-sata.c96 writel_relaxed(0x01, base + SATA_PHY_SER_CTRL); in qcom_apq8064_sata_phy_init()
97 writel_relaxed(0xB1, base + SATA_PHY_POW_DWN_CTRL0); in qcom_apq8064_sata_phy_init()
102 writel_relaxed(0x01, base + SATA_PHY_POW_DWN_CTRL0); in qcom_apq8064_sata_phy_init()
103 writel_relaxed(0x3E, base + SATA_PHY_POW_DWN_CTRL1); in qcom_apq8064_sata_phy_init()
104 writel_relaxed(0x01, base + SATA_PHY_RX_IMCAL0); in qcom_apq8064_sata_phy_init()
105 writel_relaxed(0x01, base + SATA_PHY_TX_IMCAL0); in qcom_apq8064_sata_phy_init()
106 writel_relaxed(0x02, base + SATA_PHY_TX_IMCAL2); in qcom_apq8064_sata_phy_init()
109 writel_relaxed(0x04, base + UNIPHY_PLL_REFCLK_CFG); in qcom_apq8064_sata_phy_init()
110 writel_relaxed(0x00, base + UNIPHY_PLL_PWRGEN_CFG); in qcom_apq8064_sata_phy_init()
112 writel_relaxed(0x0A, base + UNIPHY_PLL_CAL_CFG0); in qcom_apq8064_sata_phy_init()
[all …]
/Linux-v5.4/drivers/gpu/drm/meson/
Dmeson_venc.c1044 writel_relaxed(0, priv->io_base + _REG(ENCI_VIDEO_EN)); in meson_venc_hdmi_mode_set()
1045 writel_relaxed(0, priv->io_base + _REG(ENCP_VIDEO_EN)); in meson_venc_hdmi_mode_set()
1052 writel_relaxed(ENCI_CFILT_CMPT_SEL_HIGH | 0x10, in meson_venc_hdmi_mode_set()
1054 writel_relaxed(ENCI_CFILT_CMPT_CR_DLY(2) | in meson_venc_hdmi_mode_set()
1059 writel_relaxed(0, priv->io_base + _REG(VENC_DVI_SETTING)); in meson_venc_hdmi_mode_set()
1062 writel_relaxed(0, priv->io_base + _REG(ENCI_VIDEO_MODE)); in meson_venc_hdmi_mode_set()
1063 writel_relaxed(0, priv->io_base + _REG(ENCI_VIDEO_MODE_ADV)); in meson_venc_hdmi_mode_set()
1066 writel_relaxed(vmode->enci.hso_begin, in meson_venc_hdmi_mode_set()
1068 writel_relaxed(vmode->enci.hso_end, in meson_venc_hdmi_mode_set()
1072 writel_relaxed(vmode->enci.vso_even, in meson_venc_hdmi_mode_set()
[all …]
Dmeson_crtc.c97 writel_relaxed(0 << 16 | in meson_g12a_crtc_atomic_enable()
100 writel_relaxed(0 << 16 | in meson_g12a_crtc_atomic_enable()
103 writel_relaxed(crtc_state->mode.hdisplay << 16 | in meson_g12a_crtc_atomic_enable()
241 writel_relaxed(priv->viu.osd_blend_din0_scope_h, in meson_g12a_crtc_enable_osd1()
244 writel_relaxed(priv->viu.osd_blend_din0_scope_v, in meson_g12a_crtc_enable_osd1()
247 writel_relaxed(priv->viu.osb_blend0_size, in meson_g12a_crtc_enable_osd1()
250 writel_relaxed(priv->viu.osb_blend1_size, in meson_g12a_crtc_enable_osd1()
268 writel_relaxed(VD_BLEND_PREBLD_SRC_VD1 | in meson_g12a_crtc_enable_vd1()
282 writel_relaxed(priv->viu.osd1_ctrl_stat, in meson_crtc_irq()
284 writel_relaxed(priv->viu.osd1_blk0_cfg[0], in meson_crtc_irq()
[all …]
Dmeson_vpp.c59 writel_relaxed(is_horizontal ? VPP_SCALE_HORIZONTAL_COEF : 0, in meson_vpp_write_scaling_filter_coefs()
62 writel_relaxed(coefs[i], in meson_vpp_write_scaling_filter_coefs()
84 writel_relaxed(is_horizontal ? VPP_SCALE_HORIZONTAL_COEF : 0, in meson_vpp_write_vd_scaling_filter_coefs()
87 writel_relaxed(coefs[i], in meson_vpp_write_vd_scaling_filter_coefs()
95 writel_relaxed(0x108080, priv->io_base + _REG(VPP_DUMMY_DATA1)); in meson_vpp_init()
99 writel_relaxed(VPP_PPS_DUMMY_DATA_MODE, in meson_vpp_init()
101 writel_relaxed(0x1020080, in meson_vpp_init()
104 writel_relaxed(0xf, priv->io_base + _REG(DOLBY_PATH_CTRL)); in meson_vpp_init()
108 writel_relaxed(VPP_OFIFO_SIZE_DEFAULT, in meson_vpp_init()
113 writel_relaxed(VPP_POSTBLEND_HOLD_LINES(4) | VPP_PREBLEND_HOLD_LINES(4), in meson_vpp_init()
[all …]
/Linux-v5.4/drivers/media/platform/qcom/camss/
Dcamss-csiphy-3ph-1-0.c74 writel_relaxed(0x1, csiphy->base + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(0)); in csiphy_reset()
76 writel_relaxed(0x0, csiphy->base + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(0)); in csiphy_reset()
89 writel_relaxed(val, csiphy->base + in csiphy_isr()
93 writel_relaxed(0x1, csiphy->base + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(10)); in csiphy_isr()
94 writel_relaxed(0x0, csiphy->base + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(10)); in csiphy_isr()
97 writel_relaxed(0x0, csiphy->base + in csiphy_isr()
152 writel_relaxed(val, csiphy->base + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(5)); in csiphy_lanes_enable()
155 writel_relaxed(val, csiphy->base + CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(6)); in csiphy_lanes_enable()
165 writel_relaxed(val, csiphy->base + CSIPHY_3PH_LNn_CFG1(l)); in csiphy_lanes_enable()
168 writel_relaxed(val, csiphy->base + CSIPHY_3PH_LNn_CFG2(l)); in csiphy_lanes_enable()
[all …]
Dcamss-vfe-4-7.c263 writel_relaxed(bits & ~clr_bits, vfe->base + reg); in vfe_reg_clr()
270 writel_relaxed(bits | set_bits, vfe->base + reg); in vfe_reg_set()
286 writel_relaxed(BIT(31), vfe->base + VFE_0_IRQ_MASK_0); in vfe_global_reset()
288 writel_relaxed(reset_bits, vfe->base + VFE_0_GLOBAL_RESET_CMD); in vfe_global_reset()
293 writel_relaxed(VFE_0_BUS_BDG_CMD_HALT_REQ, in vfe_halt_request()
299 writel_relaxed(0x0, vfe->base + VFE_0_BUS_BDG_CMD); in vfe_halt_clear()
397 writel_relaxed(reg, vfe->base + in vfe_wm_line_based()
406 writel_relaxed(reg, vfe->base + in vfe_wm_line_based()
409 writel_relaxed(0, vfe->base + in vfe_wm_line_based()
411 writel_relaxed(0, vfe->base + in vfe_wm_line_based()
[all …]
Dcamss-csiphy-2ph-1-0.c44 writel_relaxed(0x1, csiphy->base + CAMSS_CSI_PHY_GLBL_RESET); in csiphy_reset()
46 writel_relaxed(0x0, csiphy->base + CAMSS_CSI_PHY_GLBL_RESET); in csiphy_reset()
96 writel_relaxed(0x1, csiphy->base + in csiphy_lanes_enable()
98 writel_relaxed(0x1, csiphy->base + in csiphy_lanes_enable()
103 writel_relaxed(val, csiphy->base + CAMSS_CSI_PHY_GLBL_PWR_CFG); in csiphy_lanes_enable()
106 writel_relaxed(val, csiphy->base + CAMSS_CSI_PHY_GLBL_RESET); in csiphy_lanes_enable()
114 writel_relaxed(0x10, csiphy->base + in csiphy_lanes_enable()
116 writel_relaxed(settle_cnt, csiphy->base + in csiphy_lanes_enable()
118 writel_relaxed(0x3f, csiphy->base + in csiphy_lanes_enable()
120 writel_relaxed(0x3f, csiphy->base + in csiphy_lanes_enable()
[all …]
Dcamss-vfe-4-1.c230 writel_relaxed(bits & ~clr_bits, vfe->base + reg); in vfe_reg_clr()
237 writel_relaxed(bits | set_bits, vfe->base + reg); in vfe_reg_set()
252 writel_relaxed(reset_bits, vfe->base + VFE_0_GLOBAL_RESET_CMD); in vfe_global_reset()
257 writel_relaxed(VFE_0_BUS_BDG_CMD_HALT_REQ, in vfe_halt_request()
263 writel_relaxed(0x0, vfe->base + VFE_0_BUS_BDG_CMD); in vfe_halt_clear()
347 writel_relaxed(reg, vfe->base + in vfe_wm_line_based()
356 writel_relaxed(reg, vfe->base + in vfe_wm_line_based()
359 writel_relaxed(0, vfe->base + in vfe_wm_line_based()
361 writel_relaxed(0, vfe->base + in vfe_wm_line_based()
378 writel_relaxed(reg, in vfe_wm_set_framedrop_period()
[all …]
/Linux-v5.4/drivers/clocksource/
Dtimer-gx6605s.c30 writel_relaxed(GX6605S_STATUS_CLR, base + TIMER_STATUS); in gx6605s_timer_interrupt()
42 writel_relaxed(GX6605S_CONTRL_RST, base + TIMER_CONTRL); in gx6605s_timer_set_oneshot()
45 writel_relaxed(GX6605S_CONFIG_EN | GX6605S_CONFIG_IRQ_EN, in gx6605s_timer_set_oneshot()
57 writel_relaxed(GX6605S_CONTRL_RST, base + TIMER_CONTRL); in gx6605s_timer_set_next_event()
60 writel_relaxed(ULONG_MAX - delta, base + TIMER_INI); in gx6605s_timer_set_next_event()
61 writel_relaxed(GX6605S_CONTRL_START, base + TIMER_CONTRL); in gx6605s_timer_set_next_event()
70 writel_relaxed(0, base + TIMER_CONTRL); in gx6605s_timer_shutdown()
71 writel_relaxed(0, base + TIMER_CONFIG); in gx6605s_timer_shutdown()
104 writel_relaxed(0, base + TIMER_DIV); in gx6605s_clkevt_init()
105 writel_relaxed(0, base + TIMER_CONFIG); in gx6605s_clkevt_init()
[all …]
Dtimer-lpc32xx.c79 writel_relaxed(LPC32XX_TIMER_TCR_CRST, ddata->base + LPC32XX_TIMER_TCR); in lpc32xx_clkevt_next_event()
80 writel_relaxed(delta, ddata->base + LPC32XX_TIMER_MR0); in lpc32xx_clkevt_next_event()
81 writel_relaxed(LPC32XX_TIMER_TCR_CEN, ddata->base + LPC32XX_TIMER_TCR); in lpc32xx_clkevt_next_event()
92 writel_relaxed(0, ddata->base + LPC32XX_TIMER_TCR); in lpc32xx_clkevt_shutdown()
106 writel_relaxed(0, ddata->base + LPC32XX_TIMER_TCR); in lpc32xx_clkevt_oneshot()
109 writel_relaxed(LPC32XX_TIMER_MCR_MR0I | LPC32XX_TIMER_MCR_MR0R | in lpc32xx_clkevt_oneshot()
120 writel_relaxed(LPC32XX_TIMER_MCR_MR0I | LPC32XX_TIMER_MCR_MR0R, in lpc32xx_clkevt_periodic()
127 writel_relaxed(LPC32XX_TIMER_TCR_CRST, ddata->base + LPC32XX_TIMER_TCR); in lpc32xx_clkevt_periodic()
128 writel_relaxed(ddata->ticks_per_jiffy, ddata->base + LPC32XX_TIMER_MR0); in lpc32xx_clkevt_periodic()
129 writel_relaxed(LPC32XX_TIMER_TCR_CEN, ddata->base + LPC32XX_TIMER_TCR); in lpc32xx_clkevt_periodic()
[all …]
Dtimer-atlas7.c58 writel_relaxed(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL + 4 * idx) & ~0x7, in sirfsoc_timer_count_disable()
65 writel_relaxed(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_32COUNTER_0_CTRL + 4 * idx) | 0x3, in sirfsoc_timer_count_enable()
76 writel_relaxed(BIT(cpu), sirfsoc_timer_base + SIRFSOC_TIMER_INTR_STATUS); in sirfsoc_timer_interrupt()
91 writel_relaxed((readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL) | in sirfsoc_timer_read()
108 writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_0 + in sirfsoc_timer_set_next_event()
110 writel_relaxed(delta, sirfsoc_timer_base + SIRFSOC_TIMER_MATCH_0 + in sirfsoc_timer_set_next_event()
139 writel_relaxed(sirfsoc_timer_reg_val[i], sirfsoc_timer_base + sirfsoc_timer_reg_list[i]); in sirfsoc_clocksource_resume()
141 writel_relaxed(sirfsoc_timer_reg_val[SIRFSOC_TIMER_REG_CNT - 2], in sirfsoc_clocksource_resume()
143 writel_relaxed(sirfsoc_timer_reg_val[SIRFSOC_TIMER_REG_CNT - 1], in sirfsoc_clocksource_resume()
146 writel_relaxed(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_64COUNTER_CTRL) | in sirfsoc_clocksource_resume()
[all …]
Dtimer-prima2.c66 writel_relaxed(BIT(0), sirfsoc_timer_base + SIRFSOC_TIMER_STATUS); in sirfsoc_timer_interrupt()
79 writel_relaxed(SIRFSOC_TIMER_LATCH_BIT, in sirfsoc_timer_read()
93 writel_relaxed(SIRFSOC_TIMER_LATCH_BIT, in sirfsoc_timer_set_next_event()
97 writel_relaxed(next, sirfsoc_timer_base + SIRFSOC_TIMER_MATCH_0); in sirfsoc_timer_set_next_event()
98 writel_relaxed(SIRFSOC_TIMER_LATCH_BIT, in sirfsoc_timer_set_next_event()
109 writel_relaxed(val & ~BIT(0), in sirfsoc_timer_shutdown()
118 writel_relaxed(val | BIT(0), sirfsoc_timer_base + SIRFSOC_TIMER_INT_EN); in sirfsoc_timer_set_oneshot()
126 writel_relaxed(SIRFSOC_TIMER_LATCH_BIT, in sirfsoc_clocksource_suspend()
140 writel_relaxed(sirfsoc_timer_reg_val[i], in sirfsoc_clocksource_resume()
143 writel_relaxed(sirfsoc_timer_reg_val[SIRFSOC_TIMER_REG_CNT - 2], in sirfsoc_clocksource_resume()
[all …]
Dasm9260_timer.c113 writel_relaxed(delta, priv.base + HW_MR0); in asm9260_timer_set_next_event()
115 writel_relaxed(BM_C0_EN, priv.base + HW_TCR + SET_REG); in asm9260_timer_set_next_event()
122 writel_relaxed(BM_C0_EN, priv.base + HW_TCR + CLR_REG); in __asm9260_timer_shutdown()
136 writel_relaxed(BM_MCR_RES_EN(0) | BM_MCR_STOP_EN(0), in asm9260_timer_set_oneshot()
146 writel_relaxed(BM_MCR_RES_EN(0) | BM_MCR_STOP_EN(0), in asm9260_timer_set_periodic()
149 writel_relaxed(priv.ticks_per_jiffy, priv.base + HW_MR0); in asm9260_timer_set_periodic()
151 writel_relaxed(BM_C0_EN, priv.base + HW_TCR + SET_REG); in asm9260_timer_set_periodic()
173 writel_relaxed(BM_IR_MR0, priv.base + HW_IR); in asm9260_timer_interrupt()
213 writel_relaxed(BM_DIR_DEFAULT, priv.base + HW_DIR); in asm9260_timer_init()
215 writel_relaxed(BM_PR_DISABLE, priv.base + HW_PR); in asm9260_timer_init()
[all …]
Dtimer-efm32.c53 writel_relaxed(TIMERn_CMD_STOP, ddata->base + TIMERn_CMD); in efm32_clock_event_shutdown()
62 writel_relaxed(TIMERn_CMD_STOP, ddata->base + TIMERn_CMD); in efm32_clock_event_set_oneshot()
63 writel_relaxed(TIMERn_CTRL_PRESC_1024 | in efm32_clock_event_set_oneshot()
76 writel_relaxed(TIMERn_CMD_STOP, ddata->base + TIMERn_CMD); in efm32_clock_event_set_periodic()
77 writel_relaxed(ddata->periodic_top, ddata->base + TIMERn_TOP); in efm32_clock_event_set_periodic()
78 writel_relaxed(TIMERn_CTRL_PRESC_1024 | in efm32_clock_event_set_periodic()
82 writel_relaxed(TIMERn_CMD_START, ddata->base + TIMERn_CMD); in efm32_clock_event_set_periodic()
92 writel_relaxed(TIMERn_CMD_STOP, ddata->base + TIMERn_CMD); in efm32_clock_event_set_next_event()
93 writel_relaxed(evt, ddata->base + TIMERn_CNT); in efm32_clock_event_set_next_event()
94 writel_relaxed(TIMERn_CMD_START, ddata->base + TIMERn_CMD); in efm32_clock_event_set_next_event()
[all …]
/Linux-v5.4/arch/arm/mach-hisi/
Dhotplug.c83 writel_relaxed(CPU2_ISO_CTRL << (cpu - 2), in set_cpu_hi3620()
88 writel_relaxed(0x01 << cpu, ctrl_base + SCCPUCOREEN); in set_cpu_hi3620()
93 writel_relaxed(val << cpu, ctrl_base + SCCPURSTDIS); in set_cpu_hi3620()
96 writel_relaxed(val << cpu, ctrl_base + SCCPURSTEN); in set_cpu_hi3620()
100 writel_relaxed(CPU2_ISO_CTRL << (cpu - 2), in set_cpu_hi3620()
107 writel_relaxed(val, ctrl_base + SCPERCTRL0); in set_cpu_hi3620()
112 writel_relaxed(val << cpu, ctrl_base + SCCPURSTDIS); in set_cpu_hi3620()
117 writel_relaxed(val, ctrl_base + SCPERCTRL0); in set_cpu_hi3620()
120 writel_relaxed(0x01 << cpu, ctrl_base + SCCPUCOREDIS); in set_cpu_hi3620()
124 writel_relaxed(CPU2_ISO_CTRL << (cpu - 2), in set_cpu_hi3620()
[all …]
/Linux-v5.4/drivers/crypto/ux500/cryp/
Dcryp.c147 writel_relaxed(cr_for_kse, &device_data->base->cr); in cryp_set_configuration()
218 writel_relaxed(key_value.key_value_left, in cryp_configure_key_values()
220 writel_relaxed(key_value.key_value_right, in cryp_configure_key_values()
224 writel_relaxed(key_value.key_value_left, in cryp_configure_key_values()
226 writel_relaxed(key_value.key_value_right, in cryp_configure_key_values()
230 writel_relaxed(key_value.key_value_left, in cryp_configure_key_values()
232 writel_relaxed(key_value.key_value_right, in cryp_configure_key_values()
236 writel_relaxed(key_value.key_value_left, in cryp_configure_key_values()
238 writel_relaxed(key_value.key_value_right, in cryp_configure_key_values()
265 writel_relaxed(init_vector_value.init_value_left, in cryp_configure_init_vector()
[all …]
/Linux-v5.4/drivers/soc/qcom/
Dqcom-geni-se.c193 writel_relaxed(val, base + SE_IRQ_EN); in geni_se_io_set_mode()
197 writel_relaxed(val, base + SE_GENI_DMA_MODE_EN); in geni_se_io_set_mode()
199 writel_relaxed(0, base + SE_GSI_EVENT_EN); in geni_se_io_set_mode()
208 writel_relaxed(val, base + GENI_CGC_CTRL); in geni_se_io_init()
213 writel_relaxed(val, base + SE_DMA_GENERAL_CFG); in geni_se_io_init()
215 writel_relaxed(DEFAULT_IO_OUTPUT_CTRL_MSK, base + GENI_OUTPUT_CTRL); in geni_se_io_init()
216 writel_relaxed(FORCE_DEFAULT, base + GENI_FORCE_DEFAULT_REG); in geni_se_io_init()
221 writel_relaxed(0, se->base + SE_GSI_EVENT_EN); in geni_se_irq_clear()
222 writel_relaxed(0xffffffff, se->base + SE_GENI_M_IRQ_CLEAR); in geni_se_irq_clear()
223 writel_relaxed(0xffffffff, se->base + SE_GENI_S_IRQ_CLEAR); in geni_se_irq_clear()
[all …]
/Linux-v5.4/arch/arm/mach-qcom/
Dplatsmp.c69 writel_relaxed(0, base + VDD_SC1_ARRAY_CLAMP_GFS_CTL); in scss_release_secondary()
70 writel_relaxed(0, base + SCSS_CPU1CORE_RESET); in scss_release_secondary()
71 writel_relaxed(3, base + SCSS_DBG_STATUS_CORE_PWRDUP); in scss_release_secondary()
114 writel_relaxed(0xA4, saw_reg + APCS_SAW2_VCTL); in kpssv1_release_secondary()
120 writel_relaxed(val, reg + APCS_CPU_PWR_CTL); in kpssv1_release_secondary()
122 writel_relaxed(val, reg + APCS_CPU_PWR_CTL); in kpssv1_release_secondary()
127 writel_relaxed(val, reg + APCS_CPU_PWR_CTL); in kpssv1_release_secondary()
132 writel_relaxed(val, reg + APCS_CPU_PWR_CTL); in kpssv1_release_secondary()
137 writel_relaxed(val, reg + APCS_CPU_PWR_CTL); in kpssv1_release_secondary()
142 writel_relaxed(val, reg + APCS_CPU_PWR_CTL); in kpssv1_release_secondary()
[all …]
/Linux-v5.4/drivers/mailbox/
Dpl320-ipc.c50 writel_relaxed(CHAN_MASK(source), ipc_base + IPCMxDSET(mbox)); in set_destination()
51 writel_relaxed(CHAN_MASK(source), ipc_base + IPCMxMSET(mbox)); in set_destination()
56 writel_relaxed(CHAN_MASK(source), ipc_base + IPCMxDCLEAR(mbox)); in clear_destination()
57 writel_relaxed(CHAN_MASK(source), ipc_base + IPCMxMCLEAR(mbox)); in clear_destination()
64 writel_relaxed(data[i], ipc_base + IPCMxDR(mbox, i)); in __ipc_send()
65 writel_relaxed(0x1, ipc_base + IPCMxSEND(mbox)); in __ipc_send()
106 writel_relaxed(0, ipc_base + IPCMxSEND(IPC_TX_MBOX)); in ipc_handler()
112 writel_relaxed(2, ipc_base + IPCMxSEND(IPC_RX_MBOX)); in ipc_handler()
138 writel_relaxed(0, ipc_base + IPCMxSEND(IPC_TX_MBOX)); in pl320_probe()
146 writel_relaxed(CHAN_MASK(A9_SOURCE), in pl320_probe()
[all …]
/Linux-v5.4/drivers/mmc/host/
Dmmci_qcom_dml.c64 writel_relaxed(config, base + DML_CONFIG); in qcom_dma_start()
67 writel_relaxed(data->blksz, base + DML_PRODUCER_BAM_BLOCK_SIZE); in qcom_dma_start()
70 writel_relaxed(data->blocks * data->blksz, in qcom_dma_start()
75 writel_relaxed(config, base + DML_CONFIG); in qcom_dma_start()
77 writel_relaxed(1, base + DML_PRODUCER_START); in qcom_dma_start()
84 writel_relaxed(config, base + DML_CONFIG); in qcom_dma_start()
88 writel_relaxed(config, base + DML_CONFIG); in qcom_dma_start()
90 writel_relaxed(1, base + DML_CONSUMER_START); in qcom_dma_start()
140 writel_relaxed(1, base + DML_SW_RESET); in qcom_dma_setup()
161 writel_relaxed(config, base + DML_CONFIG); in qcom_dma_setup()
[all …]
/Linux-v5.4/drivers/perf/
Dqcom_l3_pmu.c203 writel_relaxed(gang, l3pmu->regs + L3_M_BC_GANG); in qcom_l3_cache__64bit_counter_start()
207 writel_relaxed(0, l3pmu->regs + L3_HML3_PM_EVCNTR(idx + 1)); in qcom_l3_cache__64bit_counter_start()
208 writel_relaxed(0, l3pmu->regs + L3_HML3_PM_EVCNTR(idx)); in qcom_l3_cache__64bit_counter_start()
214 writel_relaxed(EVSEL(0), l3pmu->regs + L3_HML3_PM_EVTYPE(idx + 1)); in qcom_l3_cache__64bit_counter_start()
215 writel_relaxed(EVSEL(evsel), l3pmu->regs + L3_HML3_PM_EVTYPE(idx)); in qcom_l3_cache__64bit_counter_start()
218 writel_relaxed(PMCNT_RESET, l3pmu->regs + L3_HML3_PM_CNTCTL(idx + 1)); in qcom_l3_cache__64bit_counter_start()
219 writel_relaxed(PMCNTENSET(idx + 1), l3pmu->regs + L3_M_BC_CNTENSET); in qcom_l3_cache__64bit_counter_start()
220 writel_relaxed(PMCNT_RESET, l3pmu->regs + L3_HML3_PM_CNTCTL(idx)); in qcom_l3_cache__64bit_counter_start()
221 writel_relaxed(PMCNTENSET(idx), l3pmu->regs + L3_M_BC_CNTENSET); in qcom_l3_cache__64bit_counter_start()
232 writel_relaxed(PMCNTENCLR(idx), l3pmu->regs + L3_M_BC_CNTENCLR); in qcom_l3_cache__64bit_counter_stop()
[all …]
/Linux-v5.4/drivers/video/fbdev/mmp/hw/
Dmmp_ctrl.c42 writel_relaxed(~isr, ctrl->reg_base + SPU_IRQ_ISR); in ctrl_handle_irq()
126 writel_relaxed(tmp, ctrl_regs(path) + dma_ctrl(0, path->id)); in dmafetch_set_fmt()
139 writel_relaxed(win->pitch[0], &regs->v_pitch_yc); in overlay_set_win()
140 writel_relaxed(win->pitch[2] << 16 | in overlay_set_win()
143 writel_relaxed((win->ysrc << 16) | win->xsrc, &regs->v_size); in overlay_set_win()
144 writel_relaxed((win->ydst << 16) | win->xdst, &regs->v_size_z); in overlay_set_win()
145 writel_relaxed(win->ypos << 16 | win->xpos, &regs->v_start); in overlay_set_win()
147 writel_relaxed(win->pitch[0], &regs->g_pitch); in overlay_set_win()
149 writel_relaxed((win->ysrc << 16) | win->xsrc, &regs->g_size); in overlay_set_win()
150 writel_relaxed((win->ydst << 16) | win->xdst, &regs->g_size_z); in overlay_set_win()
[all …]
/Linux-v5.4/drivers/rtc/
Drtc-st-lpc.c60 writel_relaxed(1, rtc->ioaddr + LPC_WDT_OFF); in st_rtc_set_hw_alarm()
62 writel_relaxed(msb, rtc->ioaddr + LPC_LPA_MSB_OFF); in st_rtc_set_hw_alarm()
63 writel_relaxed(lsb, rtc->ioaddr + LPC_LPA_LSB_OFF); in st_rtc_set_hw_alarm()
64 writel_relaxed(1, rtc->ioaddr + LPC_LPA_START_OFF); in st_rtc_set_hw_alarm()
66 writel_relaxed(0, rtc->ioaddr + LPC_WDT_OFF); in st_rtc_set_hw_alarm()
115 writel_relaxed(lpt >> 32, rtc->ioaddr + LPC_LPT_MSB_OFF); in st_rtc_set_time()
116 writel_relaxed(lpt, rtc->ioaddr + LPC_LPT_LSB_OFF); in st_rtc_set_time()
117 writel_relaxed(1, rtc->ioaddr + LPC_LPT_START_OFF); in st_rtc_set_time()
273 writel_relaxed(1, rtc->ioaddr + LPC_WDT_OFF); in st_rtc_suspend()
274 writel_relaxed(0, rtc->ioaddr + LPC_LPA_START_OFF); in st_rtc_suspend()
[all …]
/Linux-v5.4/drivers/irqchip/
Dirq-sa11x0.c40 writel_relaxed(reg, iobase + ICMR); in sa1100_mask_irq()
49 writel_relaxed(reg, iobase + ICMR); in sa1100_unmask_irq()
100 writel_relaxed(st->icmr & 0xfffff000, iobase + ICMR); in sa1100irq_suspend()
110 writel_relaxed(st->iccr, iobase + ICCR); in sa1100irq_resume()
111 writel_relaxed(st->iclr, iobase + ICLR); in sa1100irq_resume()
113 writel_relaxed(st->icmr, iobase + ICMR); in sa1100irq_resume()
155 writel_relaxed(0, iobase + ICMR); in sa11x0_init_irq_nodt()
158 writel_relaxed(0, iobase + ICLR); in sa11x0_init_irq_nodt()
164 writel_relaxed(1, iobase + ICCR); in sa11x0_init_irq_nodt()
Dirq-gic-common.c88 writel_relaxed(val, base + confoff); in gic_configure_irq()
109 writel_relaxed(GICD_INT_ACTLOW_LVLTRIG, in gic_dist_config()
116 writel_relaxed(GICD_INT_DEF_PRI_X4, base + GIC_DIST_PRI + i); in gic_dist_config()
123 writel_relaxed(GICD_INT_EN_CLR_X32, in gic_dist_config()
125 writel_relaxed(GICD_INT_EN_CLR_X32, in gic_dist_config()
142 writel_relaxed(GICD_INT_EN_CLR_X32, in gic_cpu_config()
144 writel_relaxed(GICD_INT_EN_CLR_X32, in gic_cpu_config()
152 writel_relaxed(GICD_INT_DEF_PRI_X4, in gic_cpu_config()
156 writel_relaxed(GICD_INT_EN_SET_SGI, base + GIC_DIST_ENABLE_SET); in gic_cpu_config()

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