42 			writel_relaxed(~isr, ctrl->reg_base + SPU_IRQ_ISR);  in ctrl_handle_irq()
126 	writel_relaxed(tmp, ctrl_regs(path) + dma_ctrl(0, path->id));  in dmafetch_set_fmt()
139 		writel_relaxed(win->pitch[0], &regs->v_pitch_yc);  in overlay_set_win()
140 		writel_relaxed(win->pitch[2] << 16 |  in overlay_set_win()
143 		writel_relaxed((win->ysrc << 16) | win->xsrc, &regs->v_size);  in overlay_set_win()
144 		writel_relaxed((win->ydst << 16) | win->xdst, &regs->v_size_z);  in overlay_set_win()
145 		writel_relaxed(win->ypos << 16 | win->xpos, &regs->v_start);  in overlay_set_win()
147 		writel_relaxed(win->pitch[0], &regs->g_pitch);  in overlay_set_win()
149 		writel_relaxed((win->ysrc << 16) | win->xsrc, &regs->g_size);  in overlay_set_win()
150 		writel_relaxed((win->ydst << 16) | win->xdst, &regs->g_size_z);  in overlay_set_win()
151 		writel_relaxed(win->ypos << 16 | win->xpos, &regs->g_start);  in overlay_set_win()
183 	writel_relaxed(tmp, ctrl_regs(path) + LCD_SCLK(path));  in path_enabledisable()
236 		writel_relaxed(addr->phys[0], &regs->v_y0);  in overlay_set_addr()
237 		writel_relaxed(addr->phys[1], &regs->v_u0);  in overlay_set_addr()
238 		writel_relaxed(addr->phys[2], &regs->v_v0);  in overlay_set_addr()
240 		writel_relaxed(addr->phys[0], &regs->g_0);  in overlay_set_addr()
263 	writel_relaxed(tmp, ctrl_regs(path) + intf_ctrl(path->id));  in path_set_mode()
269 	writel_relaxed(tmp, ctrl_regs(path) + intf_rbswap_ctrl(path->id));  in path_set_mode()
271 	writel_relaxed((mode->yres << 16) | mode->xres, &regs->screen_active);  in path_set_mode()
272 	writel_relaxed((mode->left_margin << 16) | mode->right_margin,  in path_set_mode()
274 	writel_relaxed((mode->upper_margin << 16) | mode->lower_margin,  in path_set_mode()
280 	writel_relaxed((total_y << 16) | total_x, &regs->screen_size);  in path_set_mode()
288 	writel_relaxed(vsync_ctrl, &regs->vsync_ctrl);  in path_set_mode()
302 	writel_relaxed(tmp, ctrl_regs(path) + LCD_SCLK(path));  in path_set_mode()
324 	writel_relaxed(tmp, ctrl->reg_base + LCD_TOP_CTRL);  in ctrl_set_default()
333 	writel_relaxed(tmp, ctrl->reg_base + SPU_IRQ_ENA);  in ctrl_set_default()
349 		writel_relaxed(tmp, ctrl_regs(path) + SPU_IOPAD_CONTROL);  in path_set_default()
356 	writel_relaxed(tmp, ctrl_regs(path) + LCD_SCLK(path));  in path_set_default()
366 	writel_relaxed(dma_ctrl1, ctrl_regs(path) + dma_ctrl(1, path->id));  in path_set_default()
369 	writel_relaxed(0x00000000, &regs->blank_color);  in path_set_default()
370 	writel_relaxed(0x00000000, &regs->g_1);  in path_set_default()
371 	writel_relaxed(0x00000000, &regs->g_start);  in path_set_default()
383 	writel_relaxed(tmp, ctrl_regs(path) + dma_ctrl(0, path->id));  in path_set_default()