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Searched refs:tf_shift (Results 1 – 10 of 10) sorted by relevance

/Linux-v5.4/drivers/gpu/drm/amd/display/dc/dcn10/
Ddcn10_dpp_cm.c50 dpp->tf_shift->field_name, dpp->tf_mask->field_name
138 gam_regs.shifts.csc_c11 = dpp->tf_shift->CM_GAMUT_REMAP_C11; in program_gamut_remap()
140 gam_regs.shifts.csc_c12 = dpp->tf_shift->CM_GAMUT_REMAP_C12; in program_gamut_remap()
233 gam_regs.shifts.csc_c11 = dpp->tf_shift->CM_OCSC_C11; in dpp1_cm_program_color_matrix()
235 gam_regs.shifts.csc_c12 = dpp->tf_shift->CM_OCSC_C12; in dpp1_cm_program_color_matrix()
280 reg->shifts.exp_region0_lut_offset = dpp->tf_shift->CM_RGAM_RAMA_EXP_REGION0_LUT_OFFSET; in dpp1_cm_get_reg_field()
282 reg->shifts.exp_region0_num_segments = dpp->tf_shift->CM_RGAM_RAMA_EXP_REGION0_NUM_SEGMENTS; in dpp1_cm_get_reg_field()
284 reg->shifts.exp_region1_lut_offset = dpp->tf_shift->CM_RGAM_RAMA_EXP_REGION1_LUT_OFFSET; in dpp1_cm_get_reg_field()
286 reg->shifts.exp_region1_num_segments = dpp->tf_shift->CM_RGAM_RAMA_EXP_REGION1_NUM_SEGMENTS; in dpp1_cm_get_reg_field()
289 reg->shifts.field_region_end = dpp->tf_shift->CM_RGAM_RAMB_EXP_REGION_END_B; in dpp1_cm_get_reg_field()
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Ddcn10_dpp.c49 dpp->tf_shift->field_name, dpp->tf_mask->field_name
566 const struct dcn_dpp_shift *tf_shift, in dpp1_construct() argument
576 dpp->tf_shift = tf_shift; in dpp1_construct()
Ddcn10_dpp_dscl.c50 dpp->tf_shift->field_name, dpp->tf_mask->field_name
385 dpp->tf_shift->SCL_COEF_RAM_SELECT_CURRENT); in dpp1_dscl_set_scl_filter()
Ddcn10_resource.c389 static const struct dcn_dpp_shift tf_shift = { variable
596 &tf_regs[inst], &tf_shift, &tf_mask); in dcn10_dpp_create()
Ddcn10_dpp.h1348 const struct dcn_dpp_shift *tf_shift; member
1511 const struct dcn_dpp_shift *tf_shift,
/Linux-v5.4/drivers/gpu/drm/amd/display/dc/dcn20/
Ddcn20_dpp_cm.c44 dpp->tf_shift->field_name, dpp->tf_mask->field_name
210 reg->shifts.exp_region0_lut_offset = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION0_LUT_OFFSET; in dcn20_dpp_cm_get_reg_field()
212 reg->shifts.exp_region0_num_segments = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION0_NUM_SEGMENTS; in dcn20_dpp_cm_get_reg_field()
214 reg->shifts.exp_region1_lut_offset = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION1_LUT_OFFSET; in dcn20_dpp_cm_get_reg_field()
216 reg->shifts.exp_region1_num_segments = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION1_NUM_SEGMENTS; in dcn20_dpp_cm_get_reg_field()
219 reg->shifts.field_region_end = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_END_B; in dcn20_dpp_cm_get_reg_field()
221 reg->shifts.field_region_end_slope = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_END_SLOPE_B; in dcn20_dpp_cm_get_reg_field()
223 reg->shifts.field_region_end_base = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_END_BASE_B; in dcn20_dpp_cm_get_reg_field()
225 reg->shifts.field_region_linear_slope = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B; in dcn20_dpp_cm_get_reg_field()
227 reg->shifts.exp_region_start = dpp->tf_shift->CM_BLNDGAM_RAMA_EXP_REGION_START_B; in dcn20_dpp_cm_get_reg_field()
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Ddcn20_dpp.c49 dpp->tf_shift->field_name, dpp->tf_mask->field_name
499 const struct dcn2_dpp_shift *tf_shift, in dpp2_construct() argument
509 dpp->tf_shift = tf_shift; in dpp2_construct()
Ddcn20_dpp.h630 const struct dcn2_dpp_shift *tf_shift; member
703 const struct dcn2_dpp_shift *tf_shift,
Ddcn20_resource.c583 static const struct dcn2_dpp_shift tf_shift = { variable
872 &tf_regs[inst], &tf_shift, &tf_mask)) in dcn20_dpp_create()
/Linux-v5.4/drivers/gpu/drm/amd/display/dc/dcn21/
Ddcn21_resource.c610 static const struct dcn2_dpp_shift tf_shift = { variable
666 &tf_regs[inst], &tf_shift, &tf_mask)) in dcn21_dpp_create()