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/Linux-v5.4/Documentation/devicetree/bindings/reset/
Dzynq-reset.txt8 - compatible: "xlnx,zynq-reset"
12 - #reset-cells: Must be 1
18 compatible = "xlnx,zynq-reset";
20 #reset-cells = <1>;
25 0 : soft reset
26 32 : ddr reset
27 64 : topsw reset
28 96 : dmac reset
29 128: usb0 reset
30 129: usb1 reset
[all …]
Duniphier-reset.txt1 UniPhier reset controller
4 System reset
9 "socionext,uniphier-ld4-reset" - for LD4 SoC
10 "socionext,uniphier-pro4-reset" - for Pro4 SoC
11 "socionext,uniphier-sld8-reset" - for sLD8 SoC
12 "socionext,uniphier-pro5-reset" - for Pro5 SoC
13 "socionext,uniphier-pxs2-reset" - for PXs2/LD6b SoC
14 "socionext,uniphier-ld11-reset" - for LD11 SoC
15 "socionext,uniphier-ld20-reset" - for LD20 SoC
16 "socionext,uniphier-pxs3-reset" - for PXs3 SoC
[all …]
Dreset.txt3 This binding is intended to represent the hardware reset signals present
8 Hardware blocks typically receive a reset signal. This signal is generated by
9 a reset provider (e.g. power management or clock module) and received by a
10 reset consumer (the module being reset, or a module managing when a sub-
11 ordinate module is reset). This binding exists to represent the provider and
14 A reset signal is represented by the phandle of the provider, plus a reset
15 specifier - a list of DT cells that represents the reset signal within the
16 provider. The length (number of cells) and semantics of the reset specifier
17 are dictated by the binding of the reset provider, although common schemes
20 A word on where to place reset signal consumers in device tree: It is possible
[all …]
Dsnps,hsdk-reset.txt1 Binding for the Synopsys HSDK reset controller
3 This binding uses the common reset binding[1].
5 [1] Documentation/devicetree/bindings/reset/reset.txt
8 - compatible: should be "snps,hsdk-reset".
9 - reg: should always contain 2 pairs address - length: first for reset
10 configuration register and second for corresponding SW reset and status bits
12 - #reset-cells: from common reset binding; Should always be set to 1.
15 reset: reset@880 {
16 compatible = "snps,hsdk-reset";
17 #reset-cells = <1>;
[all …]
Dti-syscon-reset.txt4 Almost all SoCs have hardware modules that require reset control in addition
5 to clock and power control for their functionality. The reset control is
13 and provides reset management functionality for various hardware modules
18 Each of the reset provider/controller nodes should be a child of a syscon
27 "ti,syscon-reset"
28 - #reset-cells : Should be 1. Please see the reset consumer node below
30 - ti,reset-bits : Contains the reset control register information
31 Should contain 7 cells for each reset exposed to
33 Cell #1 : offset of the reset assert control
35 Cell #2 : bit position of the reset in the reset
[all …]
Dsnps,axs10x-reset.txt1 Binding for the AXS10x reset controller
4 to control reset signals of selected peripherals. For example DW GMAC, etc...
6 represents up-to 32 reset lines.
11 This binding uses the common reset binding[1].
13 [1] Documentation/devicetree/bindings/reset/reset.txt
16 - compatible: should be "snps,axs10x-reset".
17 - reg: should always contain pair address - length: for creg reset
19 - #reset-cells: from common reset binding; Should always be set to 1.
22 reset: reset-controller@11220 {
23 compatible = "snps,axs10x-reset";
[all …]
Dfsl,imx7-src.txt4 Please also refer to reset.txt in this directory for common reset
15 - #reset-cells: 1, see below
19 src: reset-controller@30390000 {
23 #reset-cells = <1>;
27 Specifying reset lines connected to IP modules
30 The system reset controller can be used to reset various set of
31 peripherals. Device nodes that need access to reset lines should
32 specify them as a reset phandle in their corresponding node as
33 specified in reset.txt.
43 reset-names = "pciephy", "apps";
[all …]
Dimg,pistachio-reset.txt4 This binding describes a reset controller device that is used to enable and
5 disable individual IP blocks within the Pistachio SoC using "soft reset"
8 The actual action taken when soft reset is asserted is hardware dependent.
13 Please refer to Documentation/devicetree/bindings/reset/reset.txt
14 for common reset controller binding usage.
18 - compatible: Contains "img,pistachio-reset"
20 - #reset-cells: Contains 1
31 pistachio_reset: reset-controller {
32 compatible = "img,pistachio-reset";
33 #reset-cells = <1>;
[all …]
Dxlnx,zynqmp-reset.txt2 = Zynq UltraScale+ MPSoC reset driver binding =
9 Please also refer to reset.txt in this directory for common reset
13 - compatible: "xlnx,zynqmp-reset"
14 - #reset-cells: Specifies the number of cells needed to encode reset
26 zynqmp_reset: reset-controller {
27 compatible = "xlnx,zynqmp-reset";
28 #reset-cells = <1>;
33 Specifying reset lines connected to IP modules
36 Device nodes that need access to reset lines should
37 specify them as a reset phandle in their corresponding node as
[all …]
Dbrcm,brcmstb-reset.txt1 Broadcom STB SW_INIT-style reset controller
4 Broadcom STB SoCs have a SW_INIT-style reset controller with separate
6 reset lines.
8 Please also refer to reset.txt in this directory for common reset
12 - compatible: should be brcm,brcmstb-reset
14 - #reset-cells: must be set to 1
18 reset: reset-controller@8404318 {
19 compatible = "brcm,brcmstb-reset";
21 #reset-cells = <1>;
25 resets = <&reset>;
[all …]
Dhisilicon,hi3660-reset.txt4 Please also refer to reset.txt in this directory for common reset
7 The reset controller registers are part of the system-ctl block on
12 "hisilicon,hi3660-reset" for HI3660
13 "hisilicon,hi3670-reset", "hisilicon,hi3660-reset" for HI3670
14 - hisi,rst-syscon: phandle of the reset's syscon.
15 - #reset-cells : Specifies the number of cells needed to encode a
16 reset source. The type shall be a <u32> and the value shall be 2.
18 Cell #1 : offset of the reset assert control
22 Cell #2 : bit position of the reset in the reset control register
31 compatible = "hisilicon,hi3660-reset";
[all …]
Dlantiq,reset.txt1 Lantiq XWAY SoC RCU reset controller binding
4 This binding describes a reset-controller found on the RCU module on Lantiq
12 "lantiq,danube-reset"
13 "lantiq,xrx200-reset"
16 - Offset of the reset set register
17 - Offset of the reset status register
18 - #reset-cells : Specifies the number of cells needed to encode the
19 reset line, should be 2.
20 The first cell takes the reset set bit and the
24 Example for the reset-controllers on the xRX200 SoCs:
[all …]
Dath79-reset.txt1 Binding for Qualcomm Atheros AR7xxx/AR9XXX reset controller
3 Please also refer to reset.txt in this directory for common reset
7 - compatible: has to be "qca,<soctype>-reset", "qca,ar7100-reset"
10 - #reset-cells : Specifies the number of cells needed to encode reset
15 reset-controller@1806001c {
16 compatible = "qca,ar9132-reset", "qca,ar7100-reset";
19 #reset-cells = <1>;
Dsnps,dw-reset.txt4 Please also refer to reset.txt in this directory for common reset
10 "snps,dw-high-reset" - for active high configuration
11 "snps,dw-low-reset" - for active low configuration
16 - #reset-cells: must be 1.
20 dw_rst_1: reset-controller@0000 {
21 compatible = "snps,dw-high-reset";
23 #reset-cells = <1>;
26 dw_rst_2: reset-controller@1000 {i
27 compatible = "snps,dw-low-reset";
29 #reset-cells = <1>;
Dqcom,aoss-reset.txt4 This binding describes a reset-controller found on AOSS-CC (always on subsystem)
20 - #reset-cells:
23 Definition: must be 1; cell entry represents the reset index.
27 aoss_reset: reset-controller@c2a0000 {
30 #reset-cells = <1>;
33 Specifying reset lines connected to IP modules
36 Device nodes that need access to reset lines should
37 specify them as a reset phandle in their corresponding node as
38 specified in reset.txt.
40 For list of all valid reset indicies see
[all …]
Dqcom,pdc-global.txt4 This binding describes a reset-controller found on PDC-Global (Power Domain
20 - #reset-cells:
23 Definition: must be 1; cell entry represents the reset index.
27 pdc_reset: reset-controller@b2e0000 {
30 #reset-cells = <1>;
33 PDC reset clients
36 Device nodes that need access to reset lines should
37 specify them as a reset phandle in their corresponding node as
38 specified in reset.txt.
40 For a list of all valid reset indices see
[all …]
Dti,sci-reset.txt14 This reset controller node uses the TI SCI protocol to perform the reset
20 - compatible : Should be "ti,sci-reset"
21 - #reset-cells : Should be 2. Please see the reset consumer node below for
26 Each of the reset consumer nodes should have the following properties,
31 - resets : A phandle and reset specifier pair, one pair for each reset
33 The phandle should point to the TI-SCI reset controller node,
34 and the reset specifier should have 2 cell-values. The first
36 contain the reset mask value used by system controller.
41 Please also refer to Documentation/devicetree/bindings/reset/reset.txt for
42 common reset controller usage by consumers.
[all …]
Doxnas,reset.txt4 Please also refer to reset.txt in this directory for common reset
8 - compatible: For OX810SE, should be "oxsemi,ox810se-reset"
9 For OX820, should be "oxsemi,ox820-reset"
10 - #reset-cells: 1, see below
19 - For OX810SE: include/dt-bindings/reset/oxsemi,ox810se.h
20 - For OX820: include/dt-bindings/reset/oxsemi,ox820.h
28 reset: reset-controller {
29 compatible = "oxsemi,ox810se-reset";
30 #reset-cells = <1>;
Dberlin,reset.txt1 Marvell Berlin reset controller
4 Please also refer to reset.txt in this directory for common reset
7 The reset controller node must be a sub-node of the chip controller
11 - compatible: should be "marvell,berlin2-reset"
12 - #reset-cells: must be set to 2
16 chip_rst: reset {
17 compatible = "marvell,berlin2-reset";
18 #reset-cells = <2>;
Dsirf,rstc.txt4 Please also refer to reset.txt in this directory for common reset
11 - #reset-cells: 1, see below
15 rstc: reset-controller@88010000 {
18 #reset-cells = <1>;
21 Specifying reset lines connected to IP modules
24 The reset controller(rstc) manages various reset sources. This module provides
25 reset signals for most blocks in system. Those device nodes should specify the
26 reset line on the rstc in their resets property, containing a phandle to the
27 rstc device node and a RESET_INDEX specifying which module to reset, as described
28 in reset.txt.
/Linux-v5.4/drivers/reset/
DMakefile6 obj-$(CONFIG_RESET_A10SR) += reset-a10sr.o
7 obj-$(CONFIG_RESET_ATH79) += reset-ath79.o
8 obj-$(CONFIG_RESET_AXS10X) += reset-axs10x.o
9 obj-$(CONFIG_RESET_BERLIN) += reset-berlin.o
10 obj-$(CONFIG_RESET_BRCMSTB) += reset-brcmstb.o
11 obj-$(CONFIG_RESET_HSDK) += reset-hsdk.o
12 obj-$(CONFIG_RESET_IMX7) += reset-imx7.o
13 obj-$(CONFIG_RESET_LANTIQ) += reset-lantiq.o
14 obj-$(CONFIG_RESET_LPC18XX) += reset-lpc18xx.o
15 obj-$(CONFIG_RESET_MESON) += reset-meson.o
[all …]
DKconfig11 This framework is designed to abstract reset handling of devices
12 via GPIOs or SoC-internal reset controller modules.
22 This option enables support for the external reset functions for
29 This enables the ATH79 reset controller driver that supports the
30 AR71xx SoC reset controller.
36 This enables the reset controller driver for AXS10x.
42 This enables the reset controller driver for Marvell Berlin SoCs.
45 tristate "Broadcom STB reset controller"
49 This enables the reset controller driver for Broadcom STB SoCs using
57 This enables the reset controller driver for HSDK board.
[all …]
/Linux-v5.4/Documentation/devicetree/bindings/power/reset/
Dkeystone-reset.txt1 * Device tree bindings for Texas Instruments keystone reset
3 This node is intended to allow SoC reset in case of software reset
6 The Keystone SoCs can contain up to 4 watchdog timers to reset
8 block. The Reset Mux block can be configured to cause reset or not.
10 Additionally soft or hard reset can be configured.
14 - compatible: ti,keystone-reset
18 reset control registers.
26 - ti,soft-reset: Boolean option indicating soft reset.
27 By default hard reset is used.
29 - ti,wdt-list: WDT list that can cause SoC reset. It's not related
[all …]
/Linux-v5.4/Documentation/devicetree/bindings/power/
Damlogic,meson-gx-pwrc.txt24 - resets: phandles to the reset lines needed for this power demain sequence
25 as described in ../reset/reset.txt
45 resets = <&reset RESET_VIU>,
46 <&reset RESET_VENC>,
47 <&reset RESET_VCBUS>,
48 <&reset RESET_BT656>,
49 <&reset RESET_DVIN_RESET>,
50 <&reset RESET_RDMA>,
51 <&reset RESET_VENCI>,
52 <&reset RESET_VENCP>,
[all …]
/Linux-v5.4/drivers/clk/actions/
Dowl-reset.c17 struct owl_reset *reset = to_owl_reset(rcdev); in owl_reset_assert() local
18 const struct owl_reset_map *map = &reset->reset_map[id]; in owl_reset_assert()
20 return regmap_update_bits(reset->regmap, map->reg, map->bit, 0); in owl_reset_assert()
26 struct owl_reset *reset = to_owl_reset(rcdev); in owl_reset_deassert() local
27 const struct owl_reset_map *map = &reset->reset_map[id]; in owl_reset_deassert()
29 return regmap_update_bits(reset->regmap, map->reg, map->bit, map->bit); in owl_reset_deassert()
45 struct owl_reset *reset = to_owl_reset(rcdev); in owl_reset_status() local
46 const struct owl_reset_map *map = &reset->reset_map[id]; in owl_reset_status()
50 ret = regmap_read(reset->regmap, map->reg, &reg); in owl_reset_status()
64 .reset = owl_reset_reset,

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