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Searched refs:pll6 (Results 1 – 6 of 6) sorted by relevance

/Linux-v5.4/Documentation/devicetree/bindings/clock/
Dsunxi.txt16 "allwinner,sun4i-a10-pll6-clk" - for the PLL6 clock
17 "allwinner,sun6i-a31-pll6-clk" - for the PLL6 clock on A31
99 "allwinner,sun4i-pll6-clk", "allwinner,sun6i-a31-pll6-clk",
126 For "allwinner,sun6i-a31-pll6-clk", there are 2 outputs. The first output
127 is the normal PLL6 output, or "pll6". The second output is rate doubled
164 pll6: clk@1c20028 {
166 compatible = "allwinner,sun6i-a31-pll6-clk";
169 clock-output-names = "pll6", "pll6x2";
184 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
/Linux-v5.4/Documentation/devicetree/bindings/mfd/
Dsun6i-prcm.txt26 clocks = <&osc32k>, <&osc24M>, <&pll6>, <&pll6>;
/Linux-v5.4/drivers/gpu/drm/i915/display/
Dintel_dpll_mgr.h195 u32 ebb0, ebb4, pll0, pll1, pll2, pll3, pll6, pll8, pll9, pll10, pcsdw12; member
Dintel_dpll_mgr.c1570 temp |= pll->state.hw_state.pll6; in bxt_ddi_pll_enable()
1689 hw_state->pll6 = I915_READ(BXT_PORT_PLL(phy, ch, 6)); in bxt_ddi_pll_get_hw_state()
1690 hw_state->pll6 &= PORT_PLL_PROP_COEFF_MASK | in bxt_ddi_pll_get_hw_state()
1848 dpll_hw_state->pll6 = prop_coef | PORT_PLL_INT_COEFF(int_coef); in bxt_ddi_set_dpll_hw_state()
1849 dpll_hw_state->pll6 |= PORT_PLL_GAIN_CTL(gain_ctl); in bxt_ddi_set_dpll_hw_state()
1931 hw_state->pll6, in bxt_dump_hw_state()
Dintel_display.c12811 PIPE_CONF_CHECK_X(dpll_hw_state.pll6); in intel_pipe_config_compare()
/Linux-v5.4/Documentation/devicetree/bindings/ata/
Dahci-platform.txt67 clocks = <&pll6 0>, <&ahb_gates 25>;