| /Linux-v5.4/drivers/mfd/ |
| D | sm501.c | 116 static unsigned long decode_div(unsigned long pll2, unsigned long val, in decode_div() argument
121 pll2 = 288 * MHZ; in decode_div()
123 return pll2 / div_tab[(val >> lshft) & mask]; in decode_div()
140 unsigned long pll2 = 0; in sm501_dump_clk() local
144 pll2 = 336 * MHZ; in sm501_dump_clk()
147 pll2 = 288 * MHZ; in sm501_dump_clk()
150 pll2 = 240 * MHZ; in sm501_dump_clk()
153 pll2 = 192 * MHZ; in sm501_dump_clk()
157 sdclk0 = (misct & (1<<12)) ? pll2 : 288 * MHZ; in sm501_dump_clk()
160 sdclk1 = (misct & (1<<20)) ? pll2 : 288 * MHZ; in sm501_dump_clk()
[all …]
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| /Linux-v5.4/Documentation/devicetree/bindings/clock/ |
| D | renesas,r8a73a4-cpg-clocks.txt | 17 "pll0", "pll1", "pll2", "pll2s", "pll2h", "z", "z2", "i", "m3", "b",
29 clock-output-names = "main", "pll0", "pll1", "pll2",
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| D | renesas,sh73a0-cpg-clocks.txt | 19 "pll0", "pll1", "pll2", "pll3", "dsi0phy", "dsi1phy", "zg", "m3", "b",
31 clock-output-names = "main", "pll0", "pll1", "pll2",
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| D | prima2-clock.txt | 18 pll2 3
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| D | imx28-clock.txt | 17 pll2 3
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| /Linux-v5.4/drivers/gpu/drm/hisilicon/hibmc/ |
| D | hibmc_drm_de.c | 285 u32 *pll1, u32 *pll2) in get_pll_config() argument
294 *pll2 = hibmc_pll_table[i].pll2_config_value; in get_pll_config()
301 *pll2 = CRT_PLL2_HS_25MHZ; in get_pll_config()
317 u32 pll2; /* bit[63:32] of PLL */ in display_ctrl_adjust() local
323 get_pll_config(x, y, &pll1, &pll2); in display_ctrl_adjust()
324 writel(pll2, priv->mmio + CRT_PLL2_HS); in display_ctrl_adjust()
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| /Linux-v5.4/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/ |
| D | nv04.c | 208 uint32_t pll2 = (oldpll2 & 0x7fff0000) | 1 << 31 | pv->NM2; in setPLL_double_highregs() local
218 pll2 = 0; in setPLL_double_highregs()
227 pll2 |= 0x011f; in setPLL_double_highregs()
233 if (oldpll1 == pll1 && oldpll2 == pll2) in setPLL_double_highregs()
266 nvkm_wr32(device, reg2, pll2); in setPLL_double_highregs()
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| /Linux-v5.4/drivers/gpu/drm/tegra/ |
| D | sor.c | 366 unsigned int pll2; member
1226 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_power_down()
1228 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_power_down()
1236 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_power_down()
1239 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_power_down()
1727 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_edp_enable()
1729 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_edp_enable()
1740 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_edp_enable()
1744 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_edp_enable()
1750 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_edp_enable()
[all …]
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| /Linux-v5.4/drivers/gpu/drm/nouveau/dispnv04/ |
| D | hw.c | 132 uint32_t pll2, struct nvkm_pll_vals *pllvals) in nouveau_hw_decode_pll() argument
143 pllvals->NM1 = pll2 & 0xffff; in nouveau_hw_decode_pll()
146 pllvals->NM2 = pll2 >> 16; in nouveau_hw_decode_pll()
149 if (nv_two_reg_pll(dev) && pll2 & NV31_RAMDAC_ENABLE_VCO2) in nouveau_hw_decode_pll()
150 pllvals->NM2 = pll2 & 0xffff; in nouveau_hw_decode_pll()
169 uint32_t reg1, pll1, pll2 = 0; in nouveau_hw_get_pllvals() local
179 pll2 = nvif_rd32(device, reg1 + 4); in nouveau_hw_get_pllvals()
183 pll2 = nvif_rd32(device, reg2); in nouveau_hw_get_pllvals()
192 pll2 = 0; in nouveau_hw_get_pllvals()
195 pll2 = 0; in nouveau_hw_get_pllvals()
[all …]
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| /Linux-v5.4/drivers/clk/sunxi/ |
| D | Makefile | 12 obj-$(CONFIG_CLK_SUNXI_CLOCKS) += clk-a10-pll2.o
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| /Linux-v5.4/drivers/clk/mxs/ |
| D | clk-imx28.c | 133 ref_xtal, pll0, pll1, pll2, ref_cpu, ref_emi, ref_io0, ref_io1, enumerator
170 clks[pll2] = mxs_clk_pll("pll2", "ref_xtal", PLL2CTRL0, 23, 50000000); in mx28_clocks_init()
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| /Linux-v5.4/arch/arm/boot/dts/ |
| D | ste-nomadik-stn8815.dtsi | 242 pll2: pll2@0 { label
253 clocks = <&pll2>;
268 clocks = <&pll2>;
276 clocks = <&pll2>;
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| D | dra74x.dtsi | 102 "pll2_clkctrl", "pll2";
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| D | r8a73a4.dtsi | 521 clock-output-names = "main", "pll0", "pll1", "pll2",
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| D | sh73a0.dtsi | 637 clock-output-names = "main", "pll0", "pll1", "pll2",
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| /Linux-v5.4/drivers/gpu/drm/i915/display/ |
| D | intel_dpll_mgr.h | 195 u32 ebb0, ebb4, pll0, pll1, pll2, pll3, pll6, pll8, pll9, pll10, pcsdw12; member
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| D | intel_dpll_mgr.c | 1556 temp |= pll->state.hw_state.pll2; in bxt_ddi_pll_enable()
1683 hw_state->pll2 = I915_READ(BXT_PORT_PLL(phy, ch, 2)); in bxt_ddi_pll_get_hw_state()
1684 hw_state->pll2 &= PORT_PLL_M2_FRAC_MASK; in bxt_ddi_pll_get_hw_state()
1843 dpll_hw_state->pll2 = clk_div->m2_frac; in bxt_ddi_set_dpll_hw_state()
1929 hw_state->pll2, in bxt_dump_hw_state()
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| D | intel_ddi.c | 1661 clock.m2 |= pll_state->pll2 & PORT_PLL_M2_FRAC_MASK; in bxt_calc_pll_link()
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| D | intel_display.c | 12809 PIPE_CONF_CHECK_X(dpll_hw_state.pll2); in intel_pipe_config_compare()
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| /Linux-v5.4/drivers/clk/sirf/ |
| D | clk-atlas6.c | 61 rtc, osc, pll1, pll2, pll3, mem, sys, security, dsp, gps, enumerator
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| D | clk-prima2.c | 60 rtc, osc, pll1, pll2, pll3, mem, sys, security, dsp, gps, enumerator
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| /Linux-v5.4/Documentation/devicetree/bindings/display/ti/ |
| D | ti,dra7-dss.txt | 24 'pll1', 'pll2_clkctrl', 'pll2'
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| /Linux-v5.4/sound/soc/codecs/ |
| D | tscs454.c | 132 struct pll pll2; member
293 pll_init(&tscs454->pll2, 2); in tscs454_data_init()
445 mutex_lock(&tscs454->pll2.lock); in coeff_ram_put()
467 mutex_unlock(&tscs454->pll2.lock); in coeff_ram_put()
699 mutex_lock(&tscs454->pll2.lock); in pll_connected()
700 users = tscs454->pll2.users; in pll_connected()
701 mutex_unlock(&tscs454->pll2.lock); in pll_connected()
3198 aif->pll = &tscs454->pll2; in tscs454_hw_params()
3214 tscs454->internal_rate.pll = &tscs454->pll2; in tscs454_hw_params()
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| /Linux-v5.4/arch/arm/mach-davinci/ |
| D | dm365.c | 772 void __iomem *pll1, *pll2, *psc; in dm365_init_time() local
780 pll2 = ioremap(DAVINCI_PLL2_BASE, SZ_1K); in dm365_init_time()
781 dm365_pll2_init(NULL, pll2, NULL); in dm365_init_time()
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| /Linux-v5.4/drivers/clk/qcom/ |
| D | mmcc-msm8960.c | 108 static struct clk_pll pll2 = { variable
2717 [PLL2] = &pll2.clkr,
2893 [PLL2] = &pll2.clkr,
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