366 	unsigned int pll2;  member
1226 	value = tegra_sor_readl(sor, sor->soc->regs->pll2);  in tegra_sor_power_down()
1228 	tegra_sor_writel(sor, value, sor->soc->regs->pll2);  in tegra_sor_power_down()
1236 	value = tegra_sor_readl(sor, sor->soc->regs->pll2);  in tegra_sor_power_down()
1239 	tegra_sor_writel(sor, value, sor->soc->regs->pll2);  in tegra_sor_power_down()
1727 	value = tegra_sor_readl(sor, sor->soc->regs->pll2);  in tegra_sor_edp_enable()
1729 	tegra_sor_writel(sor, value, sor->soc->regs->pll2);  in tegra_sor_edp_enable()
1740 	value = tegra_sor_readl(sor, sor->soc->regs->pll2);  in tegra_sor_edp_enable()
1744 	tegra_sor_writel(sor, value, sor->soc->regs->pll2);  in tegra_sor_edp_enable()
1750 		value = tegra_sor_readl(sor, sor->soc->regs->pll2);  in tegra_sor_edp_enable()
1757 	value = tegra_sor_readl(sor, sor->soc->regs->pll2);  in tegra_sor_edp_enable()
1760 	tegra_sor_writel(sor, value, sor->soc->regs->pll2);  in tegra_sor_edp_enable()
1773 	value = tegra_sor_readl(sor, sor->soc->regs->pll2);  in tegra_sor_edp_enable()
1776 	tegra_sor_writel(sor, value, sor->soc->regs->pll2);  in tegra_sor_edp_enable()
1794 	value = tegra_sor_readl(sor, sor->soc->regs->pll2);  in tegra_sor_edp_enable()
1796 	tegra_sor_writel(sor, value, sor->soc->regs->pll2);  in tegra_sor_edp_enable()
1806 	value = tegra_sor_readl(sor, sor->soc->regs->pll2);  in tegra_sor_edp_enable()
1808 	tegra_sor_writel(sor, value, sor->soc->regs->pll2);  in tegra_sor_edp_enable()
1813 	value = tegra_sor_readl(sor, sor->soc->regs->pll2);  in tegra_sor_edp_enable()
1815 	tegra_sor_writel(sor, value, sor->soc->regs->pll2);  in tegra_sor_edp_enable()
2456 	value = tegra_sor_readl(sor, sor->soc->regs->pll2);  in tegra_sor_hdmi_enable()
2458 	tegra_sor_writel(sor, value, sor->soc->regs->pll2);  in tegra_sor_hdmi_enable()
2471 	value = tegra_sor_readl(sor, sor->soc->regs->pll2);  in tegra_sor_hdmi_enable()
2473 	tegra_sor_writel(sor, value, sor->soc->regs->pll2);  in tegra_sor_hdmi_enable()
2477 	value = tegra_sor_readl(sor, sor->soc->regs->pll2);  in tegra_sor_hdmi_enable()
2480 	tegra_sor_writel(sor, value, sor->soc->regs->pll2);  in tegra_sor_hdmi_enable()
3040 	.pll2 = 0x19,
3065 	.pll2 = 0x19,
3109 	.pll2 = 0x165,
3151 	.pll2 = 0x16b,