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Searched refs:membase (Results 1 – 25 of 233) sorted by relevance

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/Linux-v5.4/drivers/tty/serial/
Dmilbeaut_usio.c71 writew(readw(port->membase + MLB_USIO_REG_FCR) & ~MLB_USIO_FCR_FTIE, in mlb_usio_stop_tx()
72 port->membase + MLB_USIO_REG_FCR); in mlb_usio_stop_tx()
73 writeb(readb(port->membase + MLB_USIO_REG_SCR) & ~MLB_USIO_SCR_TBIE, in mlb_usio_stop_tx()
74 port->membase + MLB_USIO_REG_SCR); in mlb_usio_stop_tx()
82 writew(readw(port->membase + MLB_USIO_REG_FCR) & ~MLB_USIO_FCR_FTIE, in mlb_usio_tx_chars()
83 port->membase + MLB_USIO_REG_FCR); in mlb_usio_tx_chars()
84 writeb(readb(port->membase + MLB_USIO_REG_SCR) & in mlb_usio_tx_chars()
86 port->membase + MLB_USIO_REG_SCR); in mlb_usio_tx_chars()
89 writew(port->x_char, port->membase + MLB_USIO_REG_DR); in mlb_usio_tx_chars()
100 (readw(port->membase + MLB_USIO_REG_FBYTE) & 0xff); in mlb_usio_tx_chars()
[all …]
Dmcf.c62 return (readb(port->membase + MCFUART_USR) & MCFUART_USR_TXEMPTY) ? in mcf_tx_empty()
73 sigs = (readb(port->membase + MCFUART_UIPR) & MCFUART_UIPR_CTS) ? in mcf_get_mctrl()
91 writeb(MCFUART_UOP_RTS, port->membase + MCFUART_UOP1); in mcf_set_mctrl()
93 writeb(MCFUART_UOP_RTS, port->membase + MCFUART_UOP0); in mcf_set_mctrl()
104 writeb(MCFUART_UCR_TXENABLE, port->membase + MCFUART_UCR); in mcf_start_tx()
106 writeb(MCFUART_UOP_RTS, port->membase + MCFUART_UOP1); in mcf_start_tx()
109 writeb(pp->imr, port->membase + MCFUART_UIMR); in mcf_start_tx()
119 writeb(pp->imr, port->membase + MCFUART_UIMR); in mcf_stop_tx()
129 writeb(pp->imr, port->membase + MCFUART_UIMR); in mcf_stop_rx()
140 writeb(MCFUART_UCR_CMDBREAKSTART, port->membase + MCFUART_UCR); in mcf_break_ctl()
[all …]
Dxilinx_uartps.c225 while ((readl(port->membase + CDNS_UART_SR) & in cdns_uart_handle_rx()
228 rxbs_status = readl(port->membase + CDNS_UART_RXBS); in cdns_uart_handle_rx()
229 data = readl(port->membase + CDNS_UART_FIFO); in cdns_uart_handle_rx()
313 writel(CDNS_UART_IXR_TXEMPTY, port->membase + CDNS_UART_IDR); in cdns_uart_handle_tx()
317 !(readl(port->membase + CDNS_UART_SR) & in cdns_uart_handle_tx()
326 port->membase + CDNS_UART_FIFO); in cdns_uart_handle_tx()
364 isrstatus = readl(port->membase + CDNS_UART_ISR); in cdns_uart_isr()
365 writel(isrstatus, port->membase + CDNS_UART_ISR); in cdns_uart_isr()
377 !(readl(port->membase + CDNS_UART_CR) & CDNS_UART_CR_RX_DIS)) in cdns_uart_isr()
466 mreg = readl(port->membase + CDNS_UART_MR); in cdns_uart_set_baud_rate()
[all …]
Dmvebu-uart.c164 st = readl(port->membase + UART_STAT); in mvebu_uart_tx_empty()
186 unsigned int ctl = readl(port->membase + UART_INTR(port)); in mvebu_uart_stop_tx()
189 writel(ctl, port->membase + UART_INTR(port)); in mvebu_uart_stop_tx()
198 writel(xmit->buf[xmit->tail], port->membase + UART_TSH(port)); in mvebu_uart_start_tx()
203 ctl = readl(port->membase + UART_INTR(port)); in mvebu_uart_start_tx()
205 writel(ctl, port->membase + UART_INTR(port)); in mvebu_uart_start_tx()
212 ctl = readl(port->membase + UART_CTRL(port)); in mvebu_uart_stop_rx()
214 writel(ctl, port->membase + UART_CTRL(port)); in mvebu_uart_stop_rx()
216 ctl = readl(port->membase + UART_INTR(port)); in mvebu_uart_stop_rx()
218 writel(ctl, port->membase + UART_INTR(port)); in mvebu_uart_stop_rx()
[all …]
Dqcom_geni_serial.c202 uport->membase = devm_platform_ioremap_resource(pdev, 0); in qcom_geni_serial_request_port()
203 if (IS_ERR(uport->membase)) in qcom_geni_serial_request_port()
204 return PTR_ERR(uport->membase); in qcom_geni_serial_request_port()
205 port->se.base = uport->membase; in qcom_geni_serial_request_port()
225 geni_ios = readl(uport->membase + SE_GENI_IOS); in qcom_geni_serial_get_mctrl()
243 writel(uart_manual_rfr, uport->membase + SE_UART_MANUAL_RFR); in qcom_geni_serial_set_mctrl()
291 reg = readl(uport->membase + offset); in qcom_geni_serial_poll_bit()
304 writel(xmit_size, uport->membase + SE_UART_TX_TRANS_LEN); in qcom_geni_serial_setup_tx()
306 writel(m_cmd, uport->membase + SE_GENI_M_CMD0); in qcom_geni_serial_setup_tx()
317 writel(M_GENI_CMD_ABORT, uport->membase + in qcom_geni_serial_poll_tx_done()
[all …]
Dtimbuart.c42 u32 ier = ioread32(port->membase + TIMBUART_IER) & ~RXFLAGS; in timbuart_stop_rx()
43 iowrite32(ier, port->membase + TIMBUART_IER); in timbuart_stop_rx()
49 u32 ier = ioread32(port->membase + TIMBUART_IER) & ~TXBAE; in timbuart_stop_tx()
50 iowrite32(ier, port->membase + TIMBUART_IER); in timbuart_stop_tx()
64 u32 isr = ioread32(port->membase + TIMBUART_ISR); in timbuart_tx_empty()
72 u8 ctl = ioread8(port->membase + TIMBUART_CTRL) | in timbuart_flush_buffer()
75 iowrite8(ctl, port->membase + TIMBUART_CTRL); in timbuart_flush_buffer()
76 iowrite32(TXBF, port->membase + TIMBUART_ISR); in timbuart_flush_buffer()
84 while (ioread32(port->membase + TIMBUART_ISR) & RXDP) { in timbuart_rx_chars()
85 u8 ch = ioread8(port->membase + TIMBUART_RXFIFO); in timbuart_rx_chars()
[all …]
Dlpc32xx_hs.c104 port->membase))) == 0) in wait_for_xmit_empty()
118 port->membase))) < 32) in wait_for_xmit_ready()
129 writel((u32)ch, LPC32XX_HSUART_FIFO(port->membase)); in lpc32xx_hsuart_console_putchar()
169 if (!port->membase) in lpc32xx_hsuart_console_setup()
248 while ((readl(LPC32XX_HSUART_LEVEL(port->membase)) > 0) && in __serial_uart_flush()
250 tmp = readl(LPC32XX_HSUART_FIFO(port->membase)); in __serial_uart_flush()
259 tmp = readl(LPC32XX_HSUART_FIFO(port->membase)); in __serial_lpc32xx_rx()
267 LPC32XX_HSUART_IIR(port->membase)); in __serial_lpc32xx_rx()
275 tmp = readl(LPC32XX_HSUART_FIFO(port->membase)); in __serial_lpc32xx_rx()
289 writel((u32)port->x_char, LPC32XX_HSUART_FIFO(port->membase)); in __serial_lpc32xx_tx()
[all …]
Dfsl_linflexuart.c152 ier = readl(port->membase + LINIER); in linflex_stop_tx()
154 writel(ier, port->membase + LINIER); in linflex_stop_tx()
161 ier = readl(port->membase + LINIER); in linflex_stop_rx()
162 writel(ier & ~LINFLEXD_LINIER_DRIE, port->membase + LINIER); in linflex_stop_rx()
173 writeb(c, sport->membase + BDRL); in linflex_transmit_buffer()
176 while (((status = readl(sport->membase + UARTSR)) & in linflex_transmit_buffer()
185 sport->membase + UARTSR); in linflex_transmit_buffer()
200 ier = readl(port->membase + LINIER); in linflex_start_tx()
201 writel(ier | LINFLEXD_LINIER_DTIE, port->membase + LINIER); in linflex_start_tx()
214 writeb(sport->x_char, sport->membase + BDRL); in linflex_txint()
[all …]
Dmeson_uart.c97 val = readl(port->membase + AML_UART_STATUS); in meson_uart_tx_empty()
106 val = readl(port->membase + AML_UART_CONTROL); in meson_uart_stop_tx()
108 writel(val, port->membase + AML_UART_CONTROL); in meson_uart_stop_tx()
115 val = readl(port->membase + AML_UART_CONTROL); in meson_uart_stop_rx()
117 writel(val, port->membase + AML_UART_CONTROL); in meson_uart_stop_rx()
129 val = readl(port->membase + AML_UART_CONTROL); in meson_uart_shutdown()
132 writel(val, port->membase + AML_UART_CONTROL); in meson_uart_shutdown()
148 while (!(readl(port->membase + AML_UART_STATUS) & AML_UART_TX_FULL)) { in meson_uart_start_tx()
150 writel(port->x_char, port->membase + AML_UART_WFIFO); in meson_uart_start_tx()
160 writel(ch, port->membase + AML_UART_WFIFO); in meson_uart_start_tx()
[all …]
Damba-pl010.c69 cr = readb(uap->port.membase + UART010_CR); in pl010_stop_tx()
71 writel(cr, uap->port.membase + UART010_CR); in pl010_stop_tx()
80 cr = readb(uap->port.membase + UART010_CR); in pl010_start_tx()
82 writel(cr, uap->port.membase + UART010_CR); in pl010_start_tx()
91 cr = readb(uap->port.membase + UART010_CR); in pl010_stop_rx()
93 writel(cr, uap->port.membase + UART010_CR); in pl010_stop_rx()
101 cr = readb(uap->port.membase + UART010_CR); in pl010_disable_ms()
103 writel(cr, uap->port.membase + UART010_CR); in pl010_disable_ms()
112 cr = readb(uap->port.membase + UART010_CR); in pl010_enable_ms()
114 writel(cr, uap->port.membase + UART010_CR); in pl010_enable_ms()
[all …]
Ddigicolor-usart.c85 return !!(readb_relaxed(port->membase + UA_STATUS_FIFO) & in digicolor_uart_tx_full()
91 return !!(readb_relaxed(port->membase + UA_STATUS_FIFO) & in digicolor_uart_rx_empty()
97 u8 int_enable = readb_relaxed(port->membase + UA_INT_ENABLE); in digicolor_uart_stop_tx()
100 writeb_relaxed(int_enable, port->membase + UA_INT_ENABLE); in digicolor_uart_stop_tx()
105 u8 int_enable = readb_relaxed(port->membase + UA_INT_ENABLE); in digicolor_uart_start_tx()
108 writeb_relaxed(int_enable, port->membase + UA_INT_ENABLE); in digicolor_uart_start_tx()
113 u8 int_enable = readb_relaxed(port->membase + UA_INT_ENABLE); in digicolor_uart_stop_rx()
116 writeb_relaxed(int_enable, port->membase + UA_INT_ENABLE); in digicolor_uart_stop_rx()
127 writeb_relaxed(UA_INT_RX, dp->port.membase + UA_INTFLAG_SET); in digicolor_rx_poll()
145 ch = readb_relaxed(port->membase + UA_EMI_REC); in digicolor_uart_rx()
[all …]
Dfsl_lpuart.c322 return readl(port->membase + off); in lpuart32_read()
324 return ioread32be(port->membase + off); in lpuart32_read()
335 writel(val, port->membase + off); in lpuart32_write()
338 iowrite32be(val, port->membase + off); in lpuart32_write()
380 temp = readb(port->membase + UARTCR2); in lpuart_stop_tx()
382 writeb(temp, port->membase + UARTCR2); in lpuart_stop_tx()
398 temp = readb(port->membase + UARTCR2); in lpuart_stop_rx()
399 writeb(temp & ~UARTCR2_RE, port->membase + UARTCR2); in lpuart_stop_rx()
551 val = readb(sport->port.membase + UARTCFIFO); in lpuart_flush_buffer()
553 writeb(val, sport->port.membase + UARTCFIFO); in lpuart_flush_buffer()
[all …]
Dlantiq.c159 __raw_writel(ASCWHBSTATE_CLRREN, port->membase + LTQ_ASC_WHBSTATE); in lqasc_stop_rx()
168 fifocnt = __raw_readl(port->membase + LTQ_ASC_FSTAT) & in lqasc_rx_chars()
172 ch = readb(port->membase + LTQ_ASC_RBUF); in lqasc_rx_chars()
173 rsr = (__raw_readl(port->membase + LTQ_ASC_STATE) in lqasc_rx_chars()
186 port->membase + LTQ_ASC_WHBSTATE); in lqasc_rx_chars()
190 port->membase + LTQ_ASC_WHBSTATE); in lqasc_rx_chars()
195 port->membase + LTQ_ASC_WHBSTATE); in lqasc_rx_chars()
233 while (((__raw_readl(port->membase + LTQ_ASC_FSTAT) & in lqasc_tx_chars()
236 writeb(port->x_char, port->membase + LTQ_ASC_TBUF); in lqasc_tx_chars()
246 port->membase + LTQ_ASC_TBUF); in lqasc_tx_chars()
[all …]
Daltera_jtaguart.c64 return (readl(port->membase + ALTERA_JTAGUART_CONTROL_REG) & in altera_jtaguart_tx_empty()
83 writel(pp->imr, port->membase + ALTERA_JTAGUART_CONTROL_REG); in altera_jtaguart_start_tx()
92 writel(pp->imr, port->membase + ALTERA_JTAGUART_CONTROL_REG); in altera_jtaguart_stop_tx()
101 writel(pp->imr, port->membase + ALTERA_JTAGUART_CONTROL_REG); in altera_jtaguart_stop_rx()
123 while ((status = readl(port->membase + ALTERA_JTAGUART_DATA_REG)) & in altera_jtaguart_rx_chars()
147 writel(port->x_char, port->membase + ALTERA_JTAGUART_DATA_REG); in altera_jtaguart_tx_chars()
155 count = (readl(port->membase + ALTERA_JTAGUART_CONTROL_REG) & in altera_jtaguart_tx_chars()
164 port->membase + ALTERA_JTAGUART_DATA_REG); in altera_jtaguart_tx_chars()
175 writel(pp->imr, port->membase + ALTERA_JTAGUART_CONTROL_REG); in altera_jtaguart_tx_chars()
186 isr = (readl(port->membase + ALTERA_JTAGUART_CONTROL_REG) >> in altera_jtaguart_interrupt()
[all …]
/Linux-v5.4/drivers/net/ethernet/allwinner/
Dsun4i-emac.c77 void __iomem *membase; member
99 reg_val = readl(db->membase + EMAC_MAC_SUPP_REG); in emac_update_speed()
103 writel(reg_val, db->membase + EMAC_MAC_SUPP_REG); in emac_update_speed()
112 reg_val = readl(db->membase + EMAC_MAC_CTL1_REG); in emac_update_duplex()
116 writel(reg_val, db->membase + EMAC_MAC_CTL1_REG); in emac_update_duplex()
194 writel(0, db->membase + EMAC_CTL_REG); in emac_reset()
196 writel(EMAC_CTL_RESET, db->membase + EMAC_CTL_REG); in emac_reset()
261 reg_val = readl(db->membase + EMAC_TX_MODE_REG); in emac_setup()
264 db->membase + EMAC_TX_MODE_REG); in emac_setup()
268 reg_val = readl(db->membase + EMAC_MAC_CTL0_REG); in emac_setup()
[all …]
/Linux-v5.4/drivers/atm/
Didt77252.h355 void __iomem *membase; /* SAR's memory base address */ member
441 #define SAR_REG_DR0 (card->membase + 0x00)
442 #define SAR_REG_DR1 (card->membase + 0x04)
443 #define SAR_REG_DR2 (card->membase + 0x08)
444 #define SAR_REG_DR3 (card->membase + 0x0C)
445 #define SAR_REG_CMD (card->membase + 0x10)
446 #define SAR_REG_CFG (card->membase + 0x14)
447 #define SAR_REG_STAT (card->membase + 0x18)
448 #define SAR_REG_RSQB (card->membase + 0x1C)
449 #define SAR_REG_RSQT (card->membase + 0x20)
[all …]
/Linux-v5.4/drivers/gpio/
Dgpio-timberdale.c35 void __iomem *membase; member
49 reg = ioread32(tgpio->membase + offset); in timbgpio_update_bit()
56 iowrite32(reg, tgpio->membase + offset); in timbgpio_update_bit()
72 value = ioread32(tgpio->membase + TGPIOVAL); in timbgpio_gpio_get()
109 iowrite32(tgpio->last_ier, tgpio->membase + TGPIO_IER); in timbgpio_irq_disable()
121 iowrite32(tgpio->last_ier, tgpio->membase + TGPIO_IER); in timbgpio_irq_enable()
137 ver = ioread32(tgpio->membase + TGPIO_VER); in timbgpio_irq_type()
141 lvr = ioread32(tgpio->membase + TGPIO_LVR); in timbgpio_irq_type()
142 flr = ioread32(tgpio->membase + TGPIO_FLR); in timbgpio_irq_type()
144 bflr = ioread32(tgpio->membase + TGPIO_BFLR); in timbgpio_irq_type()
[all …]
Dgpio-sa1100.c18 void __iomem *membase; member
41 return readl_relaxed(sa1100_gpio_chip(chip)->membase + R_GPLR) & in sa1100_gpio_get()
49 writel_relaxed(BIT(offset), sa1100_gpio_chip(chip)->membase + reg); in sa1100_gpio_set()
54 void __iomem *gpdr = sa1100_gpio_chip(chip)->membase + R_GPDR; in sa1100_get_direction()
61 void __iomem *gpdr = sa1100_gpio_chip(chip)->membase + R_GPDR; in sa1100_direction_input()
73 void __iomem *gpdr = sa1100_gpio_chip(chip)->membase + R_GPDR; in sa1100_direction_output()
101 .membase = (void *)&GPLR,
112 void *base = sgc->membase; in sa1100_update_edge_regs()
154 writel_relaxed(BIT(d->hwirq), sgc->membase + R_GEDR); in sa1100_gpio_ack()
230 void __iomem *gedr = sgc->membase + R_GEDR; in sa1100_gpio_handler()
[all …]
/Linux-v5.4/drivers/net/phy/
Dmdio-sun4i.c32 void __iomem *membase; member
43 writel((mii_id << 8) | regnum, data->membase + EMAC_MAC_MADR_REG); in sun4i_mdio_read()
45 writel(0x1, data->membase + EMAC_MAC_MCMD_REG); in sun4i_mdio_read()
49 while (readl(data->membase + EMAC_MAC_MIND_REG) & 0x1) { in sun4i_mdio_read()
56 writel(0x0, data->membase + EMAC_MAC_MCMD_REG); in sun4i_mdio_read()
58 value = readl(data->membase + EMAC_MAC_MRDD_REG); in sun4i_mdio_read()
70 writel((mii_id << 8) | regnum, data->membase + EMAC_MAC_MADR_REG); in sun4i_mdio_write()
72 writel(0x1, data->membase + EMAC_MAC_MCMD_REG); in sun4i_mdio_write()
76 while (readl(data->membase + EMAC_MAC_MIND_REG) & 0x1) { in sun4i_mdio_write()
83 writel(0x0, data->membase + EMAC_MAC_MCMD_REG); in sun4i_mdio_write()
[all …]
/Linux-v5.4/drivers/i2c/busses/
Di2c-uniphier-f.c83 void __iomem *membase; member
111 writel(*priv->buf++, priv->membase + UNIPHIER_FI2C_DTTX); in uniphier_fi2c_fill_txfifo()
125 *priv->buf++ = readl(priv->membase + UNIPHIER_FI2C_DTRX); in uniphier_fi2c_drain_rxfifo()
132 writel(priv->enabled_irqs, priv->membase + UNIPHIER_FI2C_IE); in uniphier_fi2c_set_irqs()
138 writel(mask, priv->membase + UNIPHIER_FI2C_IC); in uniphier_fi2c_clear_irqs()
146 priv->membase + UNIPHIER_FI2C_CR); in uniphier_fi2c_stop()
156 irq_status = readl(priv->membase + UNIPHIER_FI2C_INT); in uniphier_fi2c_interrupt()
215 priv->membase + UNIPHIER_FI2C_CR); in uniphier_fi2c_interrupt()
256 writel(0, priv->membase + UNIPHIER_FI2C_TBC); in uniphier_fi2c_tx_init()
259 priv->membase + UNIPHIER_FI2C_DTTX); in uniphier_fi2c_tx_init()
[all …]
/Linux-v5.4/drivers/reset/
Dreset-stm32mp1.c18 void __iomem *membase; member
36 addr = data->membase + (bank * reg_width); in stm32_reset_update()
66 reg = readl(data->membase + (bank * reg_width)); in stm32_reset_status()
86 void __iomem *membase; in stm32_reset_probe() local
94 membase = devm_ioremap_resource(dev, res); in stm32_reset_probe()
95 if (IS_ERR(membase)) in stm32_reset_probe()
96 return PTR_ERR(membase); in stm32_reset_probe()
98 data->membase = membase; in stm32_reset_probe()
Dreset-simple.c43 reg = readl(data->membase + (bank * reg_width)); in reset_simple_update()
48 writel(reg, data->membase + (bank * reg_width)); in reset_simple_update()
76 reg = readl(data->membase + (bank * reg_width)); in reset_simple_status()
141 void __iomem *membase; in reset_simple_probe() local
152 membase = devm_ioremap_resource(dev, res); in reset_simple_probe()
153 if (IS_ERR(membase)) in reset_simple_probe()
154 return PTR_ERR(membase); in reset_simple_probe()
157 data->membase = membase; in reset_simple_probe()
171 data->membase += reg_offset; in reset_simple_probe()
/Linux-v5.4/drivers/input/keyboard/
Dlocomokbd.c72 static inline void locomokbd_charge_all(unsigned long membase) in locomokbd_charge_all() argument
74 locomo_writel(0x00FF, membase + LOCOMO_KSC); in locomokbd_charge_all()
77 static inline void locomokbd_activate_all(unsigned long membase) in locomokbd_activate_all() argument
81 locomo_writel(0, membase + LOCOMO_KSC); in locomokbd_activate_all()
82 r = locomo_readl(membase + LOCOMO_KIC); in locomokbd_activate_all()
84 locomo_writel(r, membase + LOCOMO_KIC); in locomokbd_activate_all()
87 static inline void locomokbd_activate_col(unsigned long membase, int col) in locomokbd_activate_col() argument
94 locomo_writel(nbset, membase + LOCOMO_KSC); in locomokbd_activate_col()
97 static inline void locomokbd_reset_col(unsigned long membase, int col) in locomokbd_reset_col() argument
102 locomo_writel(nbset, membase + LOCOMO_KSC); in locomokbd_reset_col()
[all …]
/Linux-v5.4/drivers/dma/
Dtimb_dma.c72 void __iomem *membase; member
89 void __iomem *membase; member
118 ier = ioread32(td->membase + TIMBDMA_IER); in __td_enable_chan_irq()
122 iowrite32(ier, td->membase + TIMBDMA_IER); in __td_enable_chan_irq()
136 isr = ioread32(td->membase + TIMBDMA_ISR) & (1 << id); in __td_dma_done_ack()
138 iowrite32(isr, td->membase + TIMBDMA_ISR); in __td_dma_done_ack()
193 td_chan, td_chan->chan.chan_id, td_chan->membase); in __td_start_dma()
198 iowrite32(0, td_chan->membase + TIMBDMA_OFFS_RX_DHAR); in __td_start_dma()
199 iowrite32(td_desc->txd.phys, td_chan->membase + in __td_start_dma()
202 iowrite32(td_chan->bytes_per_line, td_chan->membase + in __td_start_dma()
[all …]
/Linux-v5.4/drivers/tty/serial/8250/
D8250_uniphier.c43 if (!device->port.membase) in uniphier_early_console_setup()
92 return (readl(p->membase + offset) >> valshift) & 0xff; in uniphier_serial_in()
123 writel(value, p->membase + offset); in uniphier_serial_out()
135 tmp = readl(p->membase + offset); in uniphier_serial_out()
138 writel(tmp, p->membase + offset); in uniphier_serial_out()
150 return readl(up->port.membase + UNIPHIER_UART_DLR); in uniphier_serial_dl_read()
155 writel(value, up->port.membase + UNIPHIER_UART_DLR); in uniphier_serial_dl_write()
164 void __iomem *membase; in uniphier_uart_probe() local
174 membase = devm_ioremap(dev, regs->start, resource_size(regs)); in uniphier_uart_probe()
175 if (!membase) in uniphier_uart_probe()
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