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Searched refs:infracfg (Results 1 – 25 of 28) sorted by relevance

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/Linux-v5.4/Documentation/devicetree/bindings/arm/mediatek/
Dmediatek,infracfg.txt1 Mediatek infracfg controller
4 The Mediatek infracfg controller provides various clocks and reset
10 - "mediatek,mt2701-infracfg", "syscon"
11 - "mediatek,mt2712-infracfg", "syscon"
13 - "mediatek,mt6797-infracfg", "syscon"
14 - "mediatek,mt7622-infracfg", "syscon"
15 - "mediatek,mt7623-infracfg", "mediatek,mt2701-infracfg", "syscon"
16 - "mediatek,mt7629-infracfg", "syscon"
17 - "mediatek,mt8135-infracfg", "syscon"
18 - "mediatek,mt8173-infracfg", "syscon"
[all …]
/Linux-v5.4/drivers/soc/mediatek/
Dmtk-infracfg.c32 int mtk_infracfg_set_bus_protection(struct regmap *infracfg, u32 mask, in mtk_infracfg_set_bus_protection() argument
39 regmap_update_bits(infracfg, INFRA_TOPAXI_PROTECTEN, mask, in mtk_infracfg_set_bus_protection()
42 regmap_write(infracfg, INFRA_TOPAXI_PROTECTEN_SET, mask); in mtk_infracfg_set_bus_protection()
44 ret = regmap_read_poll_timeout(infracfg, INFRA_TOPAXI_PROTECTSTA1, in mtk_infracfg_set_bus_protection()
63 int mtk_infracfg_clear_bus_protection(struct regmap *infracfg, u32 mask, in mtk_infracfg_clear_bus_protection() argument
70 regmap_update_bits(infracfg, INFRA_TOPAXI_PROTECTEN, mask, 0); in mtk_infracfg_clear_bus_protection()
72 regmap_write(infracfg, INFRA_TOPAXI_PROTECTEN_CLR, mask); in mtk_infracfg_clear_bus_protection()
74 ret = regmap_read_poll_timeout(infracfg, INFRA_TOPAXI_PROTECTSTA1, in mtk_infracfg_clear_bus_protection()
DMakefile3 obj-$(CONFIG_MTK_INFRACFG) += mtk-infracfg.o
Dmtk-scpsys.c142 struct regmap *infracfg; member
250 ret = mtk_infracfg_clear_bus_protection(scp->infracfg, in scpsys_power_on()
284 ret = mtk_infracfg_set_bus_protection(scp->infracfg, in scpsys_power_off()
383 scp->infracfg = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, in init_scp()
385 if (IS_ERR(scp->infracfg)) { in init_scp()
387 PTR_ERR(scp->infracfg)); in init_scp()
388 return ERR_CAST(scp->infracfg); in init_scp()
/Linux-v5.4/arch/arm64/boot/dts/mediatek/
Dmt8183.dtsi226 infracfg: syscon@10001000 { label
227 compatible = "mediatek,mt8183-infracfg", "syscon";
268 <&infracfg CLK_INFRA_PMIC_AP>;
276 clocks = <&infracfg CLK_INFRA_AUXADC>;
287 clocks = <&clk26m>, <&infracfg CLK_INFRA_UART0>;
297 clocks = <&clk26m>, <&infracfg CLK_INFRA_UART1>;
307 clocks = <&clk26m>, <&infracfg CLK_INFRA_UART2>;
317 clocks = <&infracfg CLK_INFRA_I2C6>,
318 <&infracfg CLK_INFRA_AP_DMA>;
331 clocks = <&infracfg CLK_INFRA_I2C0>,
[all …]
Dmt7622.dtsi75 clocks = <&infracfg CLK_INFRA_MUX1_SEL>,
89 clocks = <&infracfg CLK_INFRA_MUX1_SEL>,
205 infracfg: infracfg@10000000 { label
206 compatible = "mediatek,mt7622-infracfg",
217 clocks = <&infracfg CLK_INFRA_PMIC_PD>, <&pwrap_clk>;
219 resets = <&infracfg MT7622_INFRA_PMIC_WRAP_RST>;
242 infracfg = <&infracfg>;
251 clocks = <&infracfg CLK_INFRA_IRRX_PD>,
296 clocks = <&infracfg CLK_INFRA_TRNG>;
604 clocks = <&infracfg CLK_INFRA_AUDIO_PD>,
Dmt8173.dtsi160 clocks = <&infracfg CLK_INFRA_CA53SEL>,
173 clocks = <&infracfg CLK_INFRA_CA53SEL>,
186 clocks = <&infracfg CLK_INFRA_CA72SEL>,
199 clocks = <&infracfg CLK_INFRA_CA72SEL>,
344 infracfg: power-controller@10001000 { label
345 compatible = "mediatek,mt8173-infracfg", "syscon";
444 infracfg = <&infracfg>;
458 clocks = <&infracfg CLK_INFRA_CLK_13M>,
467 resets = <&infracfg MT8173_INFRA_PMIC_WRAP_RST>;
469 clocks = <&infracfg CLK_INFRA_PMICSPI>, <&infracfg CLK_INFRA_PMICWRAP>;
[all …]
Dmt2712e.dtsi252 infracfg: syscon@10001000 { label
253 compatible = "mediatek,mt2712-infracfg", "syscon";
293 infracfg = <&infracfg>;
310 clocks = <&infracfg CLK_INFRA_AO_SPI1>;
321 clocks = <&infracfg CLK_INFRA_M4U>;
338 clocks = <&infracfg CLK_INFRA_M4U>;
607 <&infracfg CLK_INFRA_AO_SPI0>;
Dmt6797.dtsi128 compatible = "mediatek,mt6797-infracfg", "syscon";
168 infracfg = <&infrasys>;
/Linux-v5.4/include/linux/soc/mediatek/
Dinfracfg.h35 int mtk_infracfg_set_bus_protection(struct regmap *infracfg, u32 mask,
37 int mtk_infracfg_clear_bus_protection(struct regmap *infracfg, u32 mask,
/Linux-v5.4/Documentation/devicetree/bindings/sound/
Dmtk-btcvsd-snd.txt7 - mediatek,infracfg: the phandles of INFRASYS
22 mediatek,infracfg = <&infrasys>;
Dmtk-afe-pcm.txt25 clocks = <&infracfg INFRA_AUDIO>,
Dmt2701-afe-pcm.txt68 clocks = <&infracfg CLK_INFRA_AUDIO>,
/Linux-v5.4/Documentation/devicetree/bindings/cpufreq/
Dcpufreq-mediatek.txt63 clocks = <&infracfg CLK_INFRA_CPUSEL>,
185 clocks = <&infracfg CLK_INFRA_CA53SEL>,
197 clocks = <&infracfg CLK_INFRA_CA53SEL>,
209 clocks = <&infracfg CLK_INFRA_CA57SEL>,
221 clocks = <&infracfg CLK_INFRA_CA57SEL>,
/Linux-v5.4/Documentation/devicetree/bindings/soc/mediatek/
Dscpsys.txt30 - infracfg: must contain a phandle to the infracfg controller
59 infracfg = <&infracfg>;
Dpwrap.txt58 resets = <&infracfg MT8135_INFRA_PMIC_WRAP_RST>,
/Linux-v5.4/arch/arm/boot/dts/
Dmt7623.dtsi80 clocks = <&infracfg CLK_INFRA_CPUSEL>,
92 clocks = <&infracfg CLK_INFRA_CPUSEL>,
104 clocks = <&infracfg CLK_INFRA_CPUSEL>,
116 clocks = <&infracfg CLK_INFRA_CPUSEL>,
234 infracfg: syscon@10001000 { label
235 compatible = "mediatek,mt7623-infracfg",
236 "mediatek,mt2701-infracfg",
277 infracfg = <&infracfg>;
303 clocks = <&infracfg CLK_INFRA_SMI>,
305 <&infracfg CLK_INFRA_SMI>;
[all …]
Dmt7629.dtsi81 infracfg: syscon@10000000 { label
82 compatible = "mediatek,mt7629-infracfg", "syscon";
102 infracfg = <&infracfg>;
134 clocks = <&infracfg CLK_INFRA_TRNG_PD>;
461 mediatek,infracfg = <&infracfg>;
Dmt8135.dtsi133 infracfg: infracfg@10001000 { label
136 compatible = "mediatek,mt8135-infracfg", "syscon";
185 resets = <&infracfg MT8135_INFRA_PMIC_WRAP_RST>,
Dmt2701.dtsi132 infracfg: syscon@10001000 { label
133 compatible = "mediatek,mt2701-infracfg", "syscon";
155 infracfg = <&infracfg>;
193 clocks = <&infracfg CLK_INFRA_SMI>,
195 <&infracfg CLK_INFRA_SMI>;
223 clocks = <&infracfg CLK_INFRA_M4U>;
435 clocks = <&infracfg CLK_INFRA_AUDIO>,
/Linux-v5.4/Documentation/devicetree/bindings/spi/
Dspi-slave-mt27xx.txt9 It's clock gate, and should be <&infracfg CLK_INFRA_AO_SPI1>.
28 clocks = <&infracfg CLK_INFRA_AO_SPI1>;
/Linux-v5.4/Documentation/devicetree/bindings/rng/
Dmtk-rng.txt20 clocks = <&infracfg CLK_INFRA_TRNG>;
/Linux-v5.4/Documentation/devicetree/bindings/media/
Dmtk-cir.txt25 clocks = <&infracfg CLK_INFRA_IRRX>;
/Linux-v5.4/Documentation/devicetree/bindings/mailbox/
Dmtk-gce.txt48 clocks = <&infracfg CLK_INFRA_GCE>;
/Linux-v5.4/Documentation/devicetree/bindings/net/
Dmediatek-net.txt34 - mediatek,infracfg: phandle to the syscon node that handles the path from

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