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Searched refs:gpu_write (Results 1 – 22 of 22) sorted by relevance

/Linux-v5.4/drivers/gpu/drm/msm/adreno/
Da3xx_gpu.c73 gpu_write(gpu, REG_A3XX_VBIF_IN_RD_LIM_CONF0, 0x10101010); in a3xx_hw_init()
74 gpu_write(gpu, REG_A3XX_VBIF_IN_RD_LIM_CONF1, 0x10101010); in a3xx_hw_init()
75 gpu_write(gpu, REG_A3XX_VBIF_OUT_RD_LIM_CONF0, 0x10101010); in a3xx_hw_init()
76 gpu_write(gpu, REG_A3XX_VBIF_OUT_WR_LIM_CONF0, 0x10101010); in a3xx_hw_init()
77 gpu_write(gpu, REG_A3XX_VBIF_DDR_OUT_MAX_BURST, 0x0000303); in a3xx_hw_init()
78 gpu_write(gpu, REG_A3XX_VBIF_IN_WR_LIM_CONF0, 0x10101010); in a3xx_hw_init()
79 gpu_write(gpu, REG_A3XX_VBIF_IN_WR_LIM_CONF1, 0x10101010); in a3xx_hw_init()
81 gpu_write(gpu, REG_A3XX_VBIF_GATE_OFF_WRREQ_EN, 0x0000ff); in a3xx_hw_init()
83 gpu_write(gpu, REG_A3XX_VBIF_ARB_CTL, 0x00000030); in a3xx_hw_init()
85 gpu_write(gpu, REG_A3XX_VBIF_OUT_AXI_AOOO_EN, 0x0000003c); in a3xx_hw_init()
[all …]
Da4xx_gpu.c37 gpu_write(gpu, REG_A4XX_RBBM_CLOCK_CTL_TP(i), 0x02222202); in a4xx_enable_hwcg()
39 gpu_write(gpu, REG_A4XX_RBBM_CLOCK_CTL2_TP(i), 0x00002222); in a4xx_enable_hwcg()
41 gpu_write(gpu, REG_A4XX_RBBM_CLOCK_HYST_TP(i), 0x0E739CE7); in a4xx_enable_hwcg()
43 gpu_write(gpu, REG_A4XX_RBBM_CLOCK_DELAY_TP(i), 0x00111111); in a4xx_enable_hwcg()
45 gpu_write(gpu, REG_A4XX_RBBM_CLOCK_CTL_SP(i), 0x22222222); in a4xx_enable_hwcg()
47 gpu_write(gpu, REG_A4XX_RBBM_CLOCK_CTL2_SP(i), 0x00222222); in a4xx_enable_hwcg()
49 gpu_write(gpu, REG_A4XX_RBBM_CLOCK_HYST_SP(i), 0x00000104); in a4xx_enable_hwcg()
51 gpu_write(gpu, REG_A4XX_RBBM_CLOCK_DELAY_SP(i), 0x00000081); in a4xx_enable_hwcg()
52 gpu_write(gpu, REG_A4XX_RBBM_CLOCK_CTL_UCHE, 0x22222222); in a4xx_enable_hwcg()
53 gpu_write(gpu, REG_A4XX_RBBM_CLOCK_CTL2_UCHE, 0x02222222); in a4xx_enable_hwcg()
[all …]
Da5xx_power.c130 gpu_write(gpu, a5xx_sequence_regs[i].reg, in a530_lm_setup()
134 gpu_write(gpu, REG_A5XX_GPMU_TEMP_SENSOR_ID, 0x60007); in a530_lm_setup()
135 gpu_write(gpu, REG_A5XX_GPMU_DELTA_TEMP_THRESHOLD, 0x01); in a530_lm_setup()
136 gpu_write(gpu, REG_A5XX_GPMU_TEMP_SENSOR_CONFIG, 0x01); in a530_lm_setup()
139 gpu_write(gpu, REG_A5XX_GPMU_GPMU_VOLTAGE, 0x80000000 | 0); in a530_lm_setup()
141 gpu_write(gpu, REG_A5XX_GPMU_BASE_LEAKAGE, a5xx_gpu->lm_leakage); in a530_lm_setup()
144 gpu_write(gpu, REG_A5XX_GPMU_GPMU_PWR_THRESHOLD, 0x80000000 | 6000); in a530_lm_setup()
146 gpu_write(gpu, REG_A5XX_GPMU_BEC_ENABLE, 0x10001FFF); in a530_lm_setup()
147 gpu_write(gpu, REG_A5XX_GDPM_CONFIG1, 0x00201FF1); in a530_lm_setup()
150 gpu_write(gpu, REG_A5XX_GPMU_BEC_ENABLE, 0x10001FFF); in a530_lm_setup()
[all …]
Da6xx_gpu.c70 gpu_write(gpu, REG_A6XX_CP_RB_WPTR, wptr); in a6xx_flush()
283 gpu_write(gpu, a6xx_hwcg[i].offset, in a6xx_set_hwcg()
289 gpu_write(gpu, REG_A6XX_RBBM_CLOCK_CNTL, state ? 0x8aa8aa02 : 0); in a6xx_set_hwcg()
384 gpu_write(gpu, REG_A6XX_RBBM_SECVID_TSB_CNTL, 0); in a6xx_hw_init()
393 gpu_write(gpu, REG_A6XX_RBBM_SECVID_TSB_TRUSTED_SIZE, 0x00000000); in a6xx_hw_init()
396 gpu_write(gpu, REG_A6XX_CP_ADDR_MODE_CNTL, 0x1); in a6xx_hw_init()
397 gpu_write(gpu, REG_A6XX_VSC_ADDR_MODE_CNTL, 0x1); in a6xx_hw_init()
398 gpu_write(gpu, REG_A6XX_GRAS_ADDR_MODE_CNTL, 0x1); in a6xx_hw_init()
399 gpu_write(gpu, REG_A6XX_RB_ADDR_MODE_CNTL, 0x1); in a6xx_hw_init()
400 gpu_write(gpu, REG_A6XX_PC_ADDR_MODE_CNTL, 0x1); in a6xx_hw_init()
[all …]
Da2xx_gpu.c72 gpu_write(gpu, REG_AXXX_CP_ME_CNTL, AXXX_CP_ME_CNTL_HALT); in a2xx_hw_init()
74 gpu_write(gpu, REG_A2XX_RBBM_PM_OVERRIDE1, 0xfffffffe); in a2xx_hw_init()
75 gpu_write(gpu, REG_A2XX_RBBM_PM_OVERRIDE2, 0xffffffff); in a2xx_hw_init()
78 gpu_write(gpu, REG_A2XX_RBBM_SOFT_RESET, 0xffffffff); in a2xx_hw_init()
80 gpu_write(gpu, REG_A2XX_RBBM_SOFT_RESET, 0x00000000); in a2xx_hw_init()
83 gpu_write(gpu, REG_A2XX_SQ_FLOW_CONTROL, 0x18000000); in a2xx_hw_init()
86 gpu_write(gpu, REG_A2XX_RBBM_CNTL, 0x00004442); in a2xx_hw_init()
89 gpu_write(gpu, REG_A2XX_MH_MMU_MPU_BASE, 0x00000000); in a2xx_hw_init()
90 gpu_write(gpu, REG_A2XX_MH_MMU_MPU_END, 0xfffff000); in a2xx_hw_init()
92 gpu_write(gpu, REG_A2XX_MH_MMU_CONFIG, A2XX_MH_MMU_CONFIG_MMU_ENABLE | in a2xx_hw_init()
[all …]
Da5xx_gpu.c43 gpu_write(gpu, REG_A5XX_CP_RB_WPTR, wptr); in a5xx_flush()
318 gpu_write(gpu, a5xx_hwcg[i].offset, in a5xx_set_hwcg()
322 gpu_write(gpu, REG_A5XX_RBBM_CLOCK_DELAY_GPMU, state ? 0x00000770 : 0); in a5xx_set_hwcg()
323 gpu_write(gpu, REG_A5XX_RBBM_CLOCK_HYST_GPMU, state ? 0x00000004 : 0); in a5xx_set_hwcg()
326 gpu_write(gpu, REG_A5XX_RBBM_CLOCK_CNTL, state ? 0xAAA8AA00 : 0); in a5xx_set_hwcg()
327 gpu_write(gpu, REG_A5XX_RBBM_ISDB_CNT, state ? 0x182 : 0x180); in a5xx_set_hwcg()
507 gpu_write(gpu, REG_A5XX_VBIF_ROUND_ROBIN_QOS_ARB, 0x00000003); in a5xx_hw_init()
510 gpu_write(gpu, REG_A5XX_VBIF_GATE_OFF_WRREQ_EN, 0x00000009); in a5xx_hw_init()
513 gpu_write(gpu, REG_A5XX_RBBM_PERFCTR_GPU_BUSY_MASKED, 0xFFFFFFFF); in a5xx_hw_init()
516 gpu_write(gpu, REG_A5XX_RBBM_AHB_CNTL0, 0x00000001); in a5xx_hw_init()
[all …]
Da6xx_gpu_state.c145 gpu_write(gpu, REG_A6XX_CP_CRASH_DUMP_CNTL, 1); in a6xx_crashdumper_run()
150 gpu_write(gpu, REG_A6XX_CP_CRASH_DUMP_CNTL, 0); in a6xx_crashdumper_run()
162 gpu_write(gpu, REG_A6XX_DBGC_CFG_DBGBUS_SEL_A, reg); in debugbus_read()
163 gpu_write(gpu, REG_A6XX_DBGC_CFG_DBGBUS_SEL_B, reg); in debugbus_read()
164 gpu_write(gpu, REG_A6XX_DBGC_CFG_DBGBUS_SEL_C, reg); in debugbus_read()
165 gpu_write(gpu, REG_A6XX_DBGC_CFG_DBGBUS_SEL_D, reg); in debugbus_read()
209 gpu_write(gpu, ctrl0, reg); in vbif_debugbus_read()
212 gpu_write(gpu, ctrl1, i); in vbif_debugbus_read()
246 gpu_write(gpu, REG_A6XX_VBIF_CLKON, in a6xx_get_vbif_debugbus_block()
250 gpu_write(gpu, REG_A6XX_VBIF_TEST_BUS1_CTRL0, 0); in a6xx_get_vbif_debugbus_block()
[all …]
Da5xx_debugfs.c21 gpu_write(gpu, REG_A5XX_CP_PFP_STAT_ADDR, i); in pfp_print()
36 gpu_write(gpu, REG_A5XX_CP_ME_STAT_ADDR, i); in me_print()
49 gpu_write(gpu, REG_A5XX_CP_MEQ_DBG_ADDR, 0); in meq_print()
64 gpu_write(gpu, REG_A5XX_CP_ROQ_DBG_ADDR, 0); in roq_print()
Da5xx_preempt.c52 gpu_write(gpu, REG_A5XX_CP_RB_WPTR, wptr); in update_wptr()
156 gpu_write(gpu, REG_A5XX_CP_CONTEXT_SWITCH_CNTL, 1); in a5xx_preempt_trigger()
Dadreno_gpu.h350 gpu_write(&gpu->base, reg - 1, data); in adreno_gpu_write()
Da6xx_gmu.c805 gpu_write(gpu, REG_A6XX_VBIF_XIN_HALT_CTRL0, 0xf); in a6xx_gmu_shutdown()
808 gpu_write(gpu, REG_A6XX_VBIF_XIN_HALT_CTRL0, 0); in a6xx_gmu_shutdown()
/Linux-v5.4/drivers/gpu/drm/panfrost/
Dpanfrost_perfcnt.c43 gpu_write(pfdev, GPU_CMD, GPU_CMD_CLEAN_CACHES); in panfrost_perfcnt_sample_done()
53 gpu_write(pfdev, GPU_PERFCNT_BASE_LO, gpuva); in panfrost_perfcnt_dump_locked()
54 gpu_write(pfdev, GPU_PERFCNT_BASE_HI, gpuva >> 32); in panfrost_perfcnt_dump_locked()
55 gpu_write(pfdev, GPU_INT_CLEAR, in panfrost_perfcnt_dump_locked()
58 gpu_write(pfdev, GPU_CMD, GPU_CMD_PERFCNT_SAMPLE); in panfrost_perfcnt_dump_locked()
109 gpu_write(pfdev, GPU_INT_CLEAR, in panfrost_perfcnt_enable_locked()
112 gpu_write(pfdev, GPU_CMD, GPU_CMD_PERFCNT_CLEAR); in panfrost_perfcnt_enable_locked()
113 gpu_write(pfdev, GPU_CMD, GPU_CMD_CLEAN_INV_CACHES); in panfrost_perfcnt_enable_locked()
138 gpu_write(pfdev, GPU_PRFCNT_JM_EN, 0xffffffff); in panfrost_perfcnt_enable_locked()
139 gpu_write(pfdev, GPU_PRFCNT_SHADER_EN, 0xffffffff); in panfrost_perfcnt_enable_locked()
[all …]
Dpanfrost_gpu.c41 gpu_write(pfdev, GPU_INT_MASK, 0); in panfrost_gpu_irq_handler()
50 gpu_write(pfdev, GPU_INT_CLEAR, state); in panfrost_gpu_irq_handler()
60 gpu_write(pfdev, GPU_INT_MASK, 0); in panfrost_gpu_soft_reset()
61 gpu_write(pfdev, GPU_INT_CLEAR, GPU_IRQ_RESET_COMPLETED); in panfrost_gpu_soft_reset()
62 gpu_write(pfdev, GPU_CMD, GPU_CMD_SOFT_RESET); in panfrost_gpu_soft_reset()
72 gpu_write(pfdev, GPU_INT_CLEAR, GPU_IRQ_MASK_ALL); in panfrost_gpu_soft_reset()
73 gpu_write(pfdev, GPU_INT_MASK, GPU_IRQ_MASK_ALL); in panfrost_gpu_soft_reset()
103 gpu_write(pfdev, GPU_SHADER_CONFIG, quirks); in panfrost_gpu_init_quirks()
112 gpu_write(pfdev, GPU_TILER_CONFIG, quirks); in panfrost_gpu_init_quirks()
125 gpu_write(pfdev, GPU_L2_MMU_CONFIG, quirks); in panfrost_gpu_init_quirks()
[all …]
Dpanfrost_regs.h317 #define gpu_write(dev, reg, data) writel(data, dev->iomem + reg) macro
/Linux-v5.4/drivers/gpu/drm/etnaviv/
Detnaviv_iommu.c96 gpu_write(gpu, VIVS_MC_MEMORY_BASE_ADDR_RA, context->global->memory_base); in etnaviv_iommuv1_restore()
97 gpu_write(gpu, VIVS_MC_MEMORY_BASE_ADDR_FE, context->global->memory_base); in etnaviv_iommuv1_restore()
98 gpu_write(gpu, VIVS_MC_MEMORY_BASE_ADDR_TX, context->global->memory_base); in etnaviv_iommuv1_restore()
99 gpu_write(gpu, VIVS_MC_MEMORY_BASE_ADDR_PEZ, context->global->memory_base); in etnaviv_iommuv1_restore()
100 gpu_write(gpu, VIVS_MC_MEMORY_BASE_ADDR_PE, context->global->memory_base); in etnaviv_iommuv1_restore()
105 gpu_write(gpu, VIVS_MC_MMU_FE_PAGE_TABLE, pgtable); in etnaviv_iommuv1_restore()
106 gpu_write(gpu, VIVS_MC_MMU_TX_PAGE_TABLE, pgtable); in etnaviv_iommuv1_restore()
107 gpu_write(gpu, VIVS_MC_MMU_PE_PAGE_TABLE, pgtable); in etnaviv_iommuv1_restore()
108 gpu_write(gpu, VIVS_MC_MMU_PEZ_PAGE_TABLE, pgtable); in etnaviv_iommuv1_restore()
109 gpu_write(gpu, VIVS_MC_MMU_RA_PAGE_TABLE, pgtable); in etnaviv_iommuv1_restore()
Detnaviv_iommu_v2.c182 gpu_write(gpu, VIVS_MMUv2_CONTROL, VIVS_MMUv2_CONTROL_ENABLE); in etnaviv_iommuv2_restore_nonsec()
195 gpu_write(gpu, VIVS_MMUv2_PTA_ADDRESS_LOW, in etnaviv_iommuv2_restore_sec()
197 gpu_write(gpu, VIVS_MMUv2_PTA_ADDRESS_HIGH, in etnaviv_iommuv2_restore_sec()
199 gpu_write(gpu, VIVS_MMUv2_PTA_CONTROL, VIVS_MMUv2_PTA_CONTROL_ENABLE); in etnaviv_iommuv2_restore_sec()
201 gpu_write(gpu, VIVS_MMUv2_NONSEC_SAFE_ADDR_LOW, in etnaviv_iommuv2_restore_sec()
203 gpu_write(gpu, VIVS_MMUv2_SEC_SAFE_ADDR_LOW, in etnaviv_iommuv2_restore_sec()
205 gpu_write(gpu, VIVS_MMUv2_SAFE_ADDRESS_CONFIG, in etnaviv_iommuv2_restore_sec()
220 gpu_write(gpu, VIVS_MMUv2_SEC_CONTROL, VIVS_MMUv2_SEC_CONTROL_ENABLE); in etnaviv_iommuv2_restore_sec()
Detnaviv_gpu.c444 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, clock | in etnaviv_gpu_load_clock()
446 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, clock); in etnaviv_gpu_load_clock()
484 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control); in etnaviv_hw_reset()
487 gpu_write(gpu, VIVS_MMUv2_AHB_CONTROL, in etnaviv_hw_reset()
492 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control); in etnaviv_hw_reset()
500 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control); in etnaviv_hw_reset()
504 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control); in etnaviv_hw_reset()
527 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control); in etnaviv_hw_reset()
564 gpu_write(gpu, VIVS_PM_POWER_CONTROLS, ppc); in etnaviv_gpu_enable_mlcg()
595 gpu_write(gpu, VIVS_PM_MODULE_CONTROLS, pmc); in etnaviv_gpu_enable_mlcg()
[all …]
Detnaviv_perfmon.c43 gpu_write(gpu, domain->profile_config, signal->data); in perf_reg_read()
59 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, clock); in pipe_reg_read()
60 gpu_write(gpu, domain->profile_config, signal->data); in pipe_reg_read()
67 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, clock); in pipe_reg_read()
Detnaviv_gpu.h150 static inline void gpu_write(struct etnaviv_gpu *gpu, u32 reg, u32 data) in gpu_write() function
/Linux-v5.4/drivers/gpu/drm/msm/
Dmsm_gpummu.c58 gpu_write(gpummu->gpu, REG_A2XX_MH_MMU_INVALIDATE, in msm_gpummu_map()
73 gpu_write(gpummu->gpu, REG_A2XX_MH_MMU_INVALIDATE, in msm_gpummu_unmap()
Dmsm_gpu.h214 static inline void gpu_write(struct msm_gpu *gpu, u32 reg, u32 data) in gpu_write() function
229 gpu_write(gpu, reg, val | or); in gpu_rmw()
/Linux-v5.4/drivers/gpu/drm/i915/gem/selftests/
Dhuge_pages.c882 static int gpu_write(struct i915_vma *vma, in gpu_write() function
967 err = gpu_write(vma, ctx, engine, dword, val); in __igt_write_huge()
1426 err = gpu_write(vma, ctx, engine, n++, 0xdeadbeaf); in igt_ppgtt_pin_update()
1555 err = gpu_write(vma, ctx, engine, n++, 0xdeadbeaf); in igt_shrink_thp()