Lines Matching refs:gpu_write
70 gpu_write(gpu, REG_A6XX_CP_RB_WPTR, wptr); in a6xx_flush()
283 gpu_write(gpu, a6xx_hwcg[i].offset, in a6xx_set_hwcg()
289 gpu_write(gpu, REG_A6XX_RBBM_CLOCK_CNTL, state ? 0x8aa8aa02 : 0); in a6xx_set_hwcg()
384 gpu_write(gpu, REG_A6XX_RBBM_SECVID_TSB_CNTL, 0); in a6xx_hw_init()
393 gpu_write(gpu, REG_A6XX_RBBM_SECVID_TSB_TRUSTED_SIZE, 0x00000000); in a6xx_hw_init()
396 gpu_write(gpu, REG_A6XX_CP_ADDR_MODE_CNTL, 0x1); in a6xx_hw_init()
397 gpu_write(gpu, REG_A6XX_VSC_ADDR_MODE_CNTL, 0x1); in a6xx_hw_init()
398 gpu_write(gpu, REG_A6XX_GRAS_ADDR_MODE_CNTL, 0x1); in a6xx_hw_init()
399 gpu_write(gpu, REG_A6XX_RB_ADDR_MODE_CNTL, 0x1); in a6xx_hw_init()
400 gpu_write(gpu, REG_A6XX_PC_ADDR_MODE_CNTL, 0x1); in a6xx_hw_init()
401 gpu_write(gpu, REG_A6XX_HLSQ_ADDR_MODE_CNTL, 0x1); in a6xx_hw_init()
402 gpu_write(gpu, REG_A6XX_VFD_ADDR_MODE_CNTL, 0x1); in a6xx_hw_init()
403 gpu_write(gpu, REG_A6XX_VPC_ADDR_MODE_CNTL, 0x1); in a6xx_hw_init()
404 gpu_write(gpu, REG_A6XX_UCHE_ADDR_MODE_CNTL, 0x1); in a6xx_hw_init()
405 gpu_write(gpu, REG_A6XX_SP_ADDR_MODE_CNTL, 0x1); in a6xx_hw_init()
406 gpu_write(gpu, REG_A6XX_TPL1_ADDR_MODE_CNTL, 0x1); in a6xx_hw_init()
407 gpu_write(gpu, REG_A6XX_RBBM_SECVID_TSB_ADDR_MODE_CNTL, 0x1); in a6xx_hw_init()
413 gpu_write(gpu, REG_A6XX_VBIF_GATE_OFF_WRREQ_EN, 0x00000009); in a6xx_hw_init()
414 gpu_write(gpu, REG_A6XX_RBBM_VBIF_CLIENT_QOS_CNTL, 0x3); in a6xx_hw_init()
417 gpu_write(gpu, REG_A6XX_RBBM_PERFCTR_GPU_BUSY_MASKED, 0xffffffff); in a6xx_hw_init()
420 gpu_write(gpu, REG_A6XX_UCHE_WRITE_RANGE_MAX_LO, 0xffffffc0); in a6xx_hw_init()
421 gpu_write(gpu, REG_A6XX_UCHE_WRITE_RANGE_MAX_HI, 0x0001ffff); in a6xx_hw_init()
422 gpu_write(gpu, REG_A6XX_UCHE_TRAP_BASE_LO, 0xfffff000); in a6xx_hw_init()
423 gpu_write(gpu, REG_A6XX_UCHE_TRAP_BASE_HI, 0x0001ffff); in a6xx_hw_init()
424 gpu_write(gpu, REG_A6XX_UCHE_WRITE_THRU_BASE_LO, 0xfffff000); in a6xx_hw_init()
425 gpu_write(gpu, REG_A6XX_UCHE_WRITE_THRU_BASE_HI, 0x0001ffff); in a6xx_hw_init()
435 gpu_write(gpu, REG_A6XX_UCHE_FILTER_CNTL, 0x804); in a6xx_hw_init()
436 gpu_write(gpu, REG_A6XX_UCHE_CACHE_WAYS, 0x4); in a6xx_hw_init()
438 gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_2, 0x010000c0); in a6xx_hw_init()
439 gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_1, 0x8040362c); in a6xx_hw_init()
442 gpu_write(gpu, REG_A6XX_CP_MEM_POOL_SIZE, 128); in a6xx_hw_init()
445 gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, (0x300 << 11)); in a6xx_hw_init()
448 gpu_write(gpu, REG_A6XX_CP_AHB_CNTL, 0x1); in a6xx_hw_init()
451 gpu_write(gpu, REG_A6XX_RBBM_PERFCTR_CNTL, 0x1); in a6xx_hw_init()
454 gpu_write(gpu, REG_A6XX_CP_PERFCTR_CP_SEL_0, PERF_CP_ALWAYS_COUNT); in a6xx_hw_init()
456 gpu_write(gpu, REG_A6XX_RB_NC_MODE_CNTL, 2 << 1); in a6xx_hw_init()
457 gpu_write(gpu, REG_A6XX_TPL1_NC_MODE_CNTL, 2 << 1); in a6xx_hw_init()
458 gpu_write(gpu, REG_A6XX_SP_NC_MODE_CNTL, 2 << 1); in a6xx_hw_init()
459 gpu_write(gpu, REG_A6XX_UCHE_MODE_CNTL, 2 << 21); in a6xx_hw_init()
462 gpu_write(gpu, REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL, in a6xx_hw_init()
465 gpu_write(gpu, REG_A6XX_UCHE_CLIENT_PF, 1); in a6xx_hw_init()
468 gpu_write(gpu, REG_A6XX_CP_PROTECT_CNTL, 0x00000003); in a6xx_hw_init()
470 gpu_write(gpu, REG_A6XX_CP_PROTECT(0), in a6xx_hw_init()
472 gpu_write(gpu, REG_A6XX_CP_PROTECT(1), A6XX_PROTECT_RW(0xae50, 0x2)); in a6xx_hw_init()
473 gpu_write(gpu, REG_A6XX_CP_PROTECT(2), A6XX_PROTECT_RW(0x9624, 0x13)); in a6xx_hw_init()
474 gpu_write(gpu, REG_A6XX_CP_PROTECT(3), A6XX_PROTECT_RW(0x8630, 0x8)); in a6xx_hw_init()
475 gpu_write(gpu, REG_A6XX_CP_PROTECT(4), A6XX_PROTECT_RW(0x9e70, 0x1)); in a6xx_hw_init()
476 gpu_write(gpu, REG_A6XX_CP_PROTECT(5), A6XX_PROTECT_RW(0x9e78, 0x187)); in a6xx_hw_init()
477 gpu_write(gpu, REG_A6XX_CP_PROTECT(6), A6XX_PROTECT_RW(0xf000, 0x810)); in a6xx_hw_init()
478 gpu_write(gpu, REG_A6XX_CP_PROTECT(7), in a6xx_hw_init()
480 gpu_write(gpu, REG_A6XX_CP_PROTECT(8), A6XX_PROTECT_RW(0x50e, 0x0)); in a6xx_hw_init()
481 gpu_write(gpu, REG_A6XX_CP_PROTECT(9), A6XX_PROTECT_RDONLY(0x50f, 0x0)); in a6xx_hw_init()
482 gpu_write(gpu, REG_A6XX_CP_PROTECT(10), A6XX_PROTECT_RW(0x510, 0x0)); in a6xx_hw_init()
483 gpu_write(gpu, REG_A6XX_CP_PROTECT(11), in a6xx_hw_init()
485 gpu_write(gpu, REG_A6XX_CP_PROTECT(12), in a6xx_hw_init()
487 gpu_write(gpu, REG_A6XX_CP_PROTECT(13), in a6xx_hw_init()
489 gpu_write(gpu, REG_A6XX_CP_PROTECT(14), A6XX_PROTECT_RW(0xe00, 0xe)); in a6xx_hw_init()
490 gpu_write(gpu, REG_A6XX_CP_PROTECT(15), A6XX_PROTECT_RW(0x8e00, 0x0)); in a6xx_hw_init()
491 gpu_write(gpu, REG_A6XX_CP_PROTECT(16), A6XX_PROTECT_RW(0x8e50, 0xf)); in a6xx_hw_init()
492 gpu_write(gpu, REG_A6XX_CP_PROTECT(17), A6XX_PROTECT_RW(0xbe02, 0x0)); in a6xx_hw_init()
493 gpu_write(gpu, REG_A6XX_CP_PROTECT(18), in a6xx_hw_init()
495 gpu_write(gpu, REG_A6XX_CP_PROTECT(19), A6XX_PROTECT_RW(0x800, 0x82)); in a6xx_hw_init()
496 gpu_write(gpu, REG_A6XX_CP_PROTECT(20), A6XX_PROTECT_RW(0x8a0, 0x8)); in a6xx_hw_init()
497 gpu_write(gpu, REG_A6XX_CP_PROTECT(21), A6XX_PROTECT_RW(0x8ab, 0x19)); in a6xx_hw_init()
498 gpu_write(gpu, REG_A6XX_CP_PROTECT(22), A6XX_PROTECT_RW(0x900, 0x4d)); in a6xx_hw_init()
499 gpu_write(gpu, REG_A6XX_CP_PROTECT(23), A6XX_PROTECT_RW(0x98d, 0x76)); in a6xx_hw_init()
500 gpu_write(gpu, REG_A6XX_CP_PROTECT(24), in a6xx_hw_init()
502 gpu_write(gpu, REG_A6XX_CP_PROTECT(25), A6XX_PROTECT_RW(0xa630, 0x0)); in a6xx_hw_init()
505 gpu_write(gpu, REG_A6XX_RBBM_INT_0_MASK, A6XX_INT_MASK); in a6xx_hw_init()
519 gpu_write(gpu, REG_A6XX_CP_SQE_CNTL, 1); in a6xx_hw_init()
544 gpu_write(gpu, REG_A6XX_RBBM_SECVID_TRUST_CNTL, 0x0); in a6xx_hw_init()
619 gpu_write(gpu, REG_A6XX_CP_SQE_STAT_ADDR, 1); in a6xx_cp_hw_err_irq()
689 gpu_write(gpu, REG_A6XX_RBBM_INT_CLEAR_CMD, status); in a6xx_irq()