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Searched refs:gpu_read (Results 1 – 23 of 23) sorted by relevance

/Linux-v5.4/drivers/gpu/drm/panfrost/
Dpanfrost_gpu.c24 u32 state = gpu_read(pfdev, GPU_INT_STAT); in panfrost_gpu_irq_handler()
25 u32 fault_status = gpu_read(pfdev, GPU_FAULT_STATUS); in panfrost_gpu_irq_handler()
31 u64 address = (u64) gpu_read(pfdev, GPU_FAULT_ADDRESS_HI) << 32; in panfrost_gpu_irq_handler()
32 address |= gpu_read(pfdev, GPU_FAULT_ADDRESS_LO); in panfrost_gpu_irq_handler()
106 quirks = gpu_read(pfdev, GPU_TILER_CONFIG); in panfrost_gpu_init_quirks()
115 quirks = gpu_read(pfdev, GPU_L2_MMU_CONFIG); in panfrost_gpu_init_quirks()
205 pfdev->features.l2_features = gpu_read(pfdev, GPU_L2_FEATURES); in panfrost_gpu_init_features()
206 pfdev->features.core_features = gpu_read(pfdev, GPU_CORE_FEATURES); in panfrost_gpu_init_features()
207 pfdev->features.tiler_features = gpu_read(pfdev, GPU_TILER_FEATURES); in panfrost_gpu_init_features()
208 pfdev->features.mem_features = gpu_read(pfdev, GPU_MEM_FEATURES); in panfrost_gpu_init_features()
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Dpanfrost_regs.h318 #define gpu_read(dev, reg) readl(dev->iomem + reg) macro
/Linux-v5.4/drivers/gpu/drm/etnaviv/
Detnaviv_gpu.c181 specs[0] = gpu_read(gpu, VIVS_HI_CHIP_SPECS); in etnaviv_hw_specs()
182 specs[1] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_2); in etnaviv_hw_specs()
183 specs[2] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_3); in etnaviv_hw_specs()
184 specs[3] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_4); in etnaviv_hw_specs()
328 chipIdentity = gpu_read(gpu, VIVS_HI_CHIP_IDENTITY); in etnaviv_hw_identify()
337 gpu->identity.model = gpu_read(gpu, VIVS_HI_CHIP_MODEL); in etnaviv_hw_identify()
338 gpu->identity.revision = gpu_read(gpu, VIVS_HI_CHIP_REV); in etnaviv_hw_identify()
353 u32 chipDate = gpu_read(gpu, VIVS_HI_CHIP_DATE); in etnaviv_hw_identify()
354 u32 chipTime = gpu_read(gpu, VIVS_HI_CHIP_TIME); in etnaviv_hw_identify()
389 gpu->identity.features = gpu_read(gpu, VIVS_HI_CHIP_FEATURE); in etnaviv_hw_identify()
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Detnaviv_perfmon.c45 return gpu_read(gpu, domain->profile_read); in perf_reg_read()
52 u32 clock = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL); in pipe_reg_read()
61 value += gpu_read(gpu, domain->profile_read); in pipe_reg_read()
83 return gpu_read(gpu, reg); in hi_total_cycle_read()
97 return gpu_read(gpu, reg); in hi_total_idle_cycle_read()
Detnaviv_iommu_v2.c172 if (gpu_read(gpu, VIVS_MMUv2_CONTROL) & VIVS_MMUv2_CONTROL_ENABLE) in etnaviv_iommuv2_restore_nonsec()
192 if (gpu_read(gpu, VIVS_MMUv2_SEC_CONTROL) & VIVS_MMUv2_SEC_CONTROL_ENABLE) in etnaviv_iommuv2_restore_sec()
Detnaviv_gpu.h155 static inline u32 gpu_read(struct etnaviv_gpu *gpu, u32 reg) in gpu_read() function
Detnaviv_sched.c104 dma_addr = gpu_read(gpu, VIVS_FE_DMA_ADDRESS); in etnaviv_sched_timedout_job()
Detnaviv_dump.c89 reg->value = gpu_read(gpu, etnaviv_dump_registers[i]); in etnaviv_core_dump_registers()
/Linux-v5.4/drivers/gpu/drm/msm/adreno/
Da5xx_gpu.c750 gpu_read(gpu, REG_A5XX_CP_SCRATCH_REG(i))); in a5xx_recover()
757 gpu_read(gpu, REG_A5XX_RBBM_SW_RESET_CMD); in a5xx_recover()
792 if (gpu_read(gpu, REG_A5XX_RBBM_STATUS) & ~A5XX_RBBM_STATUS_HI_BUSY) in _a5xx_check_idle()
799 return !(gpu_read(gpu, REG_A5XX_RBBM_INT_0_STATUS) & in _a5xx_check_idle()
820 gpu_read(gpu, REG_A5XX_RBBM_STATUS), in a5xx_idle()
821 gpu_read(gpu, REG_A5XX_RBBM_INT_0_STATUS), in a5xx_idle()
822 gpu_read(gpu, REG_A5XX_CP_RB_RPTR), in a5xx_idle()
823 gpu_read(gpu, REG_A5XX_CP_RB_WPTR)); in a5xx_idle()
835 gpu_read(gpu, REG_A5XX_CP_SCRATCH_REG(4)), in a5xx_fault_handler()
836 gpu_read(gpu, REG_A5XX_CP_SCRATCH_REG(5)), in a5xx_fault_handler()
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Da6xx_gpu.c25 if (gpu_read(gpu, REG_A6XX_RBBM_STATUS) & in _a6xx_check_idle()
29 return !(gpu_read(gpu, REG_A6XX_RBBM_INT_0_STATUS) & in _a6xx_check_idle()
42 gpu_read(gpu, REG_A6XX_RBBM_STATUS), in a6xx_idle()
43 gpu_read(gpu, REG_A6XX_RBBM_INT_0_STATUS), in a6xx_idle()
44 gpu_read(gpu, REG_A6XX_CP_RB_RPTR), in a6xx_idle()
45 gpu_read(gpu, REG_A6XX_CP_RB_WPTR)); in a6xx_idle()
273 val = gpu_read(gpu, REG_A6XX_RBBM_CLOCK_CNTL); in a6xx_set_hwcg()
564 gpu_read(gpu, REG_A6XX_RBBM_STATUS)); in a6xx_dump()
581 gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(i))); in a6xx_recover()
604 gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(4)), in a6xx_fault_handler()
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Da2xx_gpu.c209 gpu_read(gpu, REG_AXXX_CP_SCRATCH_REG0 + i)); in a2xx_recover()
217 gpu_read(gpu, REG_A2XX_RBBM_SOFT_RESET); in a2xx_recover()
241 if (spin_until(!(gpu_read(gpu, REG_A2XX_RBBM_STATUS) & in a2xx_idle()
256 mstatus = gpu_read(gpu, REG_A2XX_MASTER_INT_SIGNAL); in a2xx_irq()
259 status = gpu_read(gpu, REG_A2XX_MH_INTERRUPT_STATUS); in a2xx_irq()
263 gpu_read(gpu, REG_A2XX_MH_MMU_PAGE_FAULT)); in a2xx_irq()
269 status = gpu_read(gpu, REG_AXXX_CP_INT_STATUS); in a2xx_irq()
279 status = gpu_read(gpu, REG_A2XX_RBBM_INT_STATUS); in a2xx_irq()
386 gpu_read(gpu, REG_A2XX_RBBM_STATUS)); in a2xx_dump()
399 state->rbbm_status = gpu_read(gpu, REG_A2XX_RBBM_STATUS); in a2xx_gpu_state_get()
Da4xx_gpu.c228 val = gpu_read(gpu, REG_A4XX_RBBM_CLOCK_DELAY_HLSQ); in a4xx_hw_init()
299 gpu_read(gpu, REG_AXXX_CP_SCRATCH_REG0 + i)); in a4xx_recover()
307 gpu_read(gpu, REG_A4XX_RBBM_SW_RESET_CMD); in a4xx_recover()
336 if (spin_until(!(gpu_read(gpu, REG_A4XX_RBBM_STATUS) & in a4xx_idle()
350 status = gpu_read(gpu, REG_A4XX_RBBM_INT_0_STATUS); in a4xx_irq()
354 uint32_t reg = gpu_read(gpu, REG_A4XX_CP_PROTECT_STATUS); in a4xx_irq()
458 state->rbbm_status = gpu_read(gpu, REG_A4XX_RBBM_STATUS); in a4xx_gpu_state_get()
477 gpu_read(gpu, REG_A4XX_RBBM_STATUS)); in a4xx_dump()
495 reg = gpu_read(gpu, REG_A4XX_RBBM_POWER_STATUS); in a4xx_pm_resume()
Da5xx_debugfs.c23 gpu_read(gpu, REG_A5XX_CP_PFP_STAT_DATA)); in pfp_print()
38 gpu_read(gpu, REG_A5XX_CP_ME_STAT_DATA)); in me_print()
53 gpu_read(gpu, REG_A5XX_CP_MEQ_DBG_DATA)); in meq_print()
70 val[j] = gpu_read(gpu, REG_A5XX_CP_ROQ_DBG_DATA); in roq_print()
Da3xx_gpu.c299 gpu_read(gpu, REG_AXXX_CP_SCRATCH_REG0 + i)); in a3xx_recover()
307 gpu_read(gpu, REG_A3XX_RBBM_SW_RESET_CMD); in a3xx_recover()
336 if (spin_until(!(gpu_read(gpu, REG_A3XX_RBBM_STATUS) & in a3xx_idle()
351 status = gpu_read(gpu, REG_A3XX_RBBM_INT_0_STATUS); in a3xx_irq()
405 gpu_read(gpu, REG_A3XX_RBBM_STATUS)); in a3xx_dump()
418 state->rbbm_status = gpu_read(gpu, REG_A3XX_RBBM_STATUS); in a3xx_gpu_state_get()
Da6xx_gpu_state.c170 data[0] = gpu_read(gpu, REG_A6XX_DBGC_CFG_DBGBUS_TRACE_BUF2); in debugbus_read()
171 data[1] = gpu_read(gpu, REG_A6XX_DBGC_CFG_DBGBUS_TRACE_BUF1); in debugbus_read()
213 data[i] = gpu_read(gpu, REG_A6XX_VBIF_TEST_BUS_OUT); in vbif_debugbus_read()
243 clk = gpu_read(gpu, REG_A6XX_VBIF_CLKON); in a6xx_get_vbif_debugbus_block()
711 obj->data[index++] = gpu_read(gpu, in a6xx_get_ahb_gpu_registers()
826 obj->data[i] = gpu_read(gpu, indexed->data); in a6xx_get_indexed_regs()
846 mempool_size = gpu_read(gpu, REG_A6XX_CP_MEM_POOL_SIZE); in a6xx_get_indexed_registers()
Da5xx_gpu.h135 if ((gpu_read(gpu, reg) & mask) == value) in spin_usecs()
Da5xx_preempt.c179 status = gpu_read(gpu, REG_A5XX_CP_CONTEXT_SWITCH_CNTL); in a5xx_preempt_irq()
Da5xx_power.c267 u32 val = gpu_read(gpu, REG_A5XX_GPMU_GENERAL_1); in a5xx_gpmu_init()
Dadreno_gpu.h341 val = gpu_read(&gpu->base, reg - 1); in adreno_gpu_read()
Dadreno_gpu.c578 state->registers[pos++] = gpu_read(gpu, addr); in adreno_gpu_state_get()
796 uint32_t val = gpu_read(gpu, addr); in adreno_dump()
Da6xx_gmu.c806 spin_until((gpu_read(gpu, REG_A6XX_VBIF_XIN_HALT_CTRL1) & 0xf) in a6xx_gmu_shutdown()
/Linux-v5.4/drivers/gpu/drm/msm/
Dmsm_gpu.h219 static inline u32 gpu_read(struct msm_gpu *gpu, u32 reg) in gpu_read() function
226 uint32_t val = gpu_read(gpu, reg); in gpu_rmw()
Dmsm_gpu.c561 current_cntrs[i] = gpu_read(gpu, gpu->perfcntrs[i].sample_reg); in update_hw_cntrs()