181 		specs[0] = gpu_read(gpu, VIVS_HI_CHIP_SPECS);  in etnaviv_hw_specs()
182 		specs[1] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_2);  in etnaviv_hw_specs()
183 		specs[2] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_3);  in etnaviv_hw_specs()
184 		specs[3] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_4);  in etnaviv_hw_specs()
328 	chipIdentity = gpu_read(gpu, VIVS_HI_CHIP_IDENTITY);  in etnaviv_hw_identify()
337 		gpu->identity.model = gpu_read(gpu, VIVS_HI_CHIP_MODEL);  in etnaviv_hw_identify()
338 		gpu->identity.revision = gpu_read(gpu, VIVS_HI_CHIP_REV);  in etnaviv_hw_identify()
353 			u32 chipDate = gpu_read(gpu, VIVS_HI_CHIP_DATE);  in etnaviv_hw_identify()
354 			u32 chipTime = gpu_read(gpu, VIVS_HI_CHIP_TIME);  in etnaviv_hw_identify()
389 	gpu->identity.features = gpu_read(gpu, VIVS_HI_CHIP_FEATURE);  in etnaviv_hw_identify()
412 				gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_0);  in etnaviv_hw_identify()
417 				gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_1);  in etnaviv_hw_identify()
419 				gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_2);  in etnaviv_hw_identify()
421 				gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_3);  in etnaviv_hw_identify()
423 				gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_4);  in etnaviv_hw_identify()
425 				gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_5);  in etnaviv_hw_identify()
459 		u32 clock = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL);  in etnaviv_gpu_update_clock()
507 		idle = gpu_read(gpu, VIVS_HI_IDLE_STATE);  in etnaviv_hw_reset()
516 		control = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL);  in etnaviv_hw_reset()
534 		idle = gpu_read(gpu, VIVS_HI_IDLE_STATE);  in etnaviv_hw_reset()
535 		control = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL);  in etnaviv_hw_reset()
556 	ppc = gpu_read(gpu, VIVS_PM_POWER_CONTROLS);  in etnaviv_gpu_enable_mlcg()
566 	pmc = gpu_read(gpu, VIVS_PM_MODULE_CONTROLS);  in etnaviv_gpu_enable_mlcg()
651 		pulse_eater = gpu_read(gpu, VIVS_PM_PULSE_EATER);  in etnaviv_gpu_setup_pulse_eater()
662 	    gpu_read(gpu, VIVS_HI_CHIP_TIME) != 0x2062400) {  in etnaviv_gpu_hw_init()
665 		mc_memory_debug = gpu_read(gpu, VIVS_MC_DEBUG_MEMORY) & ~0xff;  in etnaviv_gpu_hw_init()
688 		u32 bus_config = gpu_read(gpu, VIVS_MC_BUS_CONFIG);  in etnaviv_gpu_hw_init()
697 		u32 val = gpu_read(gpu, VIVS_MMUv2_AHB_CONTROL);  in etnaviv_gpu_hw_init()
820 	debug->address[0] = gpu_read(gpu, VIVS_FE_DMA_ADDRESS);  in verify_dma()
821 	debug->state[0]   = gpu_read(gpu, VIVS_FE_DMA_DEBUG_STATE);  in verify_dma()
824 		debug->address[1] = gpu_read(gpu, VIVS_FE_DMA_ADDRESS);  in verify_dma()
825 		debug->state[1]   = gpu_read(gpu, VIVS_FE_DMA_DEBUG_STATE);  in verify_dma()
847 	dma_lo = gpu_read(gpu, VIVS_FE_DMA_LOW);  in etnaviv_gpu_debugfs()
848 	dma_hi = gpu_read(gpu, VIVS_FE_DMA_HIGH);  in etnaviv_gpu_debugfs()
849 	axi = gpu_read(gpu, VIVS_HI_AXI_STATUS);  in etnaviv_gpu_debugfs()
850 	idle = gpu_read(gpu, VIVS_HI_IDLE_STATE);  in etnaviv_gpu_debugfs()
937 		u32 read0 = gpu_read(gpu, VIVS_MC_DEBUG_READ0);  in etnaviv_gpu_debugfs()
938 		u32 read1 = gpu_read(gpu, VIVS_MC_DEBUG_READ1);  in etnaviv_gpu_debugfs()
939 		u32 write = gpu_read(gpu, VIVS_MC_DEBUG_WRITE);  in etnaviv_gpu_debugfs()
1223 	val = gpu_read(gpu, VIVS_PM_POWER_CONTROLS);  in sync_point_perfmon_sample_pre()
1228 	val = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL);  in sync_point_perfmon_sample_pre()
1251 	val = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL);  in sync_point_perfmon_sample_post()
1256 	val = gpu_read(gpu, VIVS_PM_POWER_CONTROLS);  in sync_point_perfmon_sample_post()
1342 	u32 addr = gpu_read(gpu, VIVS_FE_DMA_ADDRESS);  in sync_point_worker()
1362 	status = gpu_read(gpu, status_reg);  in dump_mmu_fault()
1377 				    gpu_read(gpu, address_reg));  in dump_mmu_fault()
1386 	u32 intr = gpu_read(gpu, VIVS_HI_INTR_ACKNOWLEDGE);  in irq_handler()
1506 		u32 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE);  in etnaviv_gpu_wait_idle()
1809 	idle = gpu_read(gpu, VIVS_HI_IDLE_STATE) & mask;  in etnaviv_gpu_rpm_suspend()