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Searched refs:dpp_base (Results 1 – 10 of 10) sorted by relevance

/Linux-v5.4/drivers/gpu/drm/amd/display/dc/dcn20/
Ddcn20_dpp_cm.c51 struct dpp *dpp_base) in dpp2_enable_cm_block() argument
53 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); in dpp2_enable_cm_block()
57 if (dpp_base->ctx->dc->debug.cm_in_bypass) in dpp2_enable_cm_block()
65 struct dpp *dpp_base, in dpp2_degamma_ram_inuse() argument
70 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); in dpp2_degamma_ram_inuse()
86 struct dpp *dpp_base, in dpp2_program_degamma_lut() argument
93 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); in dpp2_program_degamma_lut()
117 struct dpp *dpp_base, in dpp2_set_degamma_pwl() argument
122 dpp1_power_on_degamma_lut(dpp_base, true); in dpp2_set_degamma_pwl()
123 dpp2_enable_cm_block(dpp_base); in dpp2_set_degamma_pwl()
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Ddcn20_dpp.c51 void dpp20_read_state(struct dpp *dpp_base, in dpp20_read_state() argument
54 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); in dpp20_read_state()
76 struct dpp *dpp_base, in dpp2_power_on_obuf() argument
79 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); in dpp2_power_on_obuf()
91 struct dpp *dpp_base, in dpp2_dummy_program_input_lut() argument
96 struct dpp *dpp_base, in dpp2_cnv_setup() argument
103 struct dcn20_dpp *dpp = TO_DCN20_DPP(dpp_base); in dpp2_cnv_setup()
234 dpp1_program_input_csc(dpp_base, color_space, select, &tbl_entry); in dpp2_cnv_setup()
236 dpp1_program_input_csc(dpp_base, color_space, select, NULL); in dpp2_cnv_setup()
245 dpp2_power_on_obuf(dpp_base, true); in dpp2_cnv_setup()
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Ddcn20_hwseq.c694 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; in dcn20_set_blend_lut() local
704 &dpp_base->regamma_params, false); in dcn20_set_blend_lut()
705 blend_lut = &dpp_base->regamma_params; in dcn20_set_blend_lut()
708 result = dpp_base->funcs->dpp_program_blnd_lut(dpp_base, blend_lut); in dcn20_set_blend_lut()
716 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; in dcn20_set_shaper_3dlut() local
726 &dpp_base->shaper_params, true); in dcn20_set_shaper_3dlut()
727 shaper_lut = &dpp_base->shaper_params; in dcn20_set_shaper_3dlut()
731 result = dpp_base->funcs->dpp_program_shaper_lut(dpp_base, shaper_lut); in dcn20_set_shaper_3dlut()
734 result = dpp_base->funcs->dpp_program_3dlut(dpp_base, in dcn20_set_shaper_3dlut()
737 result = dpp_base->funcs->dpp_program_3dlut(dpp_base, NULL); in dcn20_set_shaper_3dlut()
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Ddcn20_dpp.h645 void dpp20_read_state(struct dpp *dpp_base,
649 struct dpp *dpp_base,
653 struct dpp *dpp_base,
657 struct dpp *dpp_base, const struct pwl_params *params);
660 struct dpp *dpp_base,
664 struct dpp *dpp_base,
668 struct dpp *dpp_base,
678 struct dpp *dpp_base,
682 struct dpp *dpp_base,
691 struct dpp *dpp_base,
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/Linux-v5.4/drivers/gpu/drm/amd/display/dc/dcn10/
Ddcn10_dpp_cm.c181 struct dpp *dpp_base, in dpp1_cm_set_gamut_remap() argument
184 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); in dpp1_cm_set_gamut_remap()
260 struct dpp *dpp_base, in dpp1_cm_set_output_csc_default() argument
263 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); in dpp1_cm_set_output_csc_default()
330 struct dpp *dpp_base, in dpp1_cm_set_output_csc_adjustment() argument
333 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); in dpp1_cm_set_output_csc_adjustment()
338 void dpp1_cm_power_on_regamma_lut(struct dpp *dpp_base, in dpp1_cm_power_on_regamma_lut() argument
341 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); in dpp1_cm_power_on_regamma_lut()
348 void dpp1_cm_program_regamma_lut(struct dpp *dpp_base, in dpp1_cm_program_regamma_lut() argument
353 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); in dpp1_cm_program_regamma_lut()
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Ddcn10_dpp.c94 void dpp_read_state(struct dpp *dpp_base, in dpp_read_state() argument
97 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); in dpp_read_state()
203 void dpp_reset(struct dpp *dpp_base) in dpp_reset() argument
205 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); in dpp_reset()
219 struct dpp *dpp_base, const struct pwl_params *params, enum opp_regamma mode) in dpp1_cm_set_regamma_pwl() argument
221 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); in dpp1_cm_set_regamma_pwl()
239 dpp1_cm_power_on_regamma_lut(dpp_base, true); in dpp1_cm_set_regamma_pwl()
240 dpp1_cm_configure_regamma_lut(dpp_base, dpp->is_write_to_ram_a_safe); in dpp1_cm_set_regamma_pwl()
243 dpp1_cm_program_regamma_luta_settings(dpp_base, params); in dpp1_cm_set_regamma_pwl()
245 dpp1_cm_program_regamma_lutb_settings(dpp_base, params); in dpp1_cm_set_regamma_pwl()
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Ddcn10_dpp_dscl.c168 struct dpp *dpp_base, in dpp1_dscl_get_dscl_mode() argument
174 if (dpp_base->caps->dscl_data_proc_format == DSCL_DATA_PRCESSING_FIXED_FORMAT) { in dpp1_dscl_get_dscl_mode()
527 struct dpp *dpp_base, in dpp1_dscl_set_scaler_auto_scale() argument
531 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); in dpp1_dscl_set_scaler_auto_scale()
533 dpp_base, scl_data, dpp_base->ctx->dc->debug.always_scale); in dpp1_dscl_set_scaler_auto_scale()
666 struct dpp *dpp_base, in dpp1_dscl_set_scaler_manual_scale() argument
670 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); in dpp1_dscl_set_scaler_manual_scale()
672 dpp_base, scl_data, dpp_base->ctx->dc->debug.always_scale); in dpp1_dscl_set_scaler_manual_scale()
Ddcn10_dpp.h1370 struct dpp *dpp_base,
1374 struct dpp *dpp_base,
1381 struct dpp *dpp_base,
1396 struct dpp *dpp_base,
1400 struct dpp *dpp_base,
1404 struct dpp *dpp_base,
1408 struct dpp *dpp_base,
1414 struct dpp *dpp_base,
1418 struct dpp *dpp_base,
1424 struct dpp *dpp_base,
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Ddcn10_hw_sequencer.c1392 struct dpp *dpp_base = pipe_ctx->plane_res.dpp; in dcn10_set_input_transfer_func() local
1396 if (dpp_base == NULL) in dcn10_set_input_transfer_func()
1403 !dpp_base->ctx->dc->debug.always_use_regamma in dcn10_set_input_transfer_func()
1406 dpp_base->funcs->dpp_program_input_lut(dpp_base, plane_state->gamma_correction); in dcn10_set_input_transfer_func()
1409 dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_BYPASS); in dcn10_set_input_transfer_func()
1413 dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_HW_sRGB); in dcn10_set_input_transfer_func()
1416 dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_HW_xvYCC); in dcn10_set_input_transfer_func()
1419 dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_BYPASS); in dcn10_set_input_transfer_func()
1427 dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_BYPASS); in dcn10_set_input_transfer_func()
1430 &dpp_base->degamma_params); in dcn10_set_input_transfer_func()
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/Linux-v5.4/drivers/gpu/drm/amd/display/dc/inc/hw/
Ddpp.h111 void (*dpp_program_cm_dealpha)(struct dpp *dpp_base,
115 struct dpp *dpp_base,
178 struct dpp *dpp_base,
182 struct dpp *dpp_base,
185 void (*dpp_program_degamma_pwl)(struct dpp *dpp_base,
189 struct dpp *dpp_base,
200 void (*dpp_full_bypass)(struct dpp *dpp_base);
203 struct dpp *dpp_base,
207 struct dpp *dpp_base,
215 struct dpp *dpp_base,
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