Searched refs:clk_hw_get_flags (Results 1 – 25 of 25) sorted by relevance
96 if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) { in ccu_gate_round_rate()
90 if (clk_hw_get_flags(hw) & CLK_SET_RATE_NO_REPARENT) { in ccu_mux_helper_determine_rate()
111 if (!(clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT)) { in ccu_mp_round_rate()
75 if (!(clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT)) { in __bestmult()
38 if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) { in clk_factor_round_rate()
303 if (!(clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT)) { in clk_divider_bestdiv()368 if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) { in divider_ro_round_rate_parent()
67 if (clk_hw_get_flags(hw) & CLK_SET_RATE_NO_REPARENT) { in clk_composite_determine_rate()
667 if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) { in si5351_msynth_round_rate()1046 if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) { in si5351_clkout_round_rate()
307 if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) { in cdce706_divider_round_rate()
674 if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) { in si5341_output_clk_round_rate()
439 if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) { in clk_apb_mul_round_rate()
505 unsigned long clk_hw_get_flags(const struct clk_hw *hw) in clk_hw_get_flags() function509 EXPORT_SYMBOL_GPL(clk_hw_get_flags);
128 if ((clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) && divider->is_frac) in zynqmp_clk_divider_round_rate()
63 if (!(clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT)) in sclk_div_bestdiv()
127 if (clk_hw_get_flags(clk) & CLK_SET_RATE_PARENT) in sun9i_a80_cpus_clk_determine_rate()
106 if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) in clk_factors_determine_rate()
79 if (!(clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT)) { in owl_clk_val_best()
48 if (!(clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT)) { in clk_half_divider_bestdiv()
123 if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) { in flexgen_round_rate()
825 unsigned long clk_hw_get_flags(const struct clk_hw *hw);827 (clk_hw_get_flags((hw)) & CLK_SET_RATE_PARENT)
185 if (!(clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT)) { in ti_clk_divider_bestdiv()
147 if (!(clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT)) { in davinci_pll_determine_rate()
415 clk_flags = clk_hw_get_flags(hw); in _freq_tbl_determine_rate()
218 clk_flags = clk_hw_get_flags(hw); in _freq_tbl_determine_rate()
979 if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) in clk_alpha_pll_postdiv_round_ro_rate()