Searched refs:clk_csr (Results 1 – 12 of 12) sorted by relevance
86 value |= (priv->clk_csr << priv->hw->mii.clk_csr_shift) in stmmac_xgmac2_mdio_read()126 value |= (priv->clk_csr << priv->hw->mii.clk_csr_shift) in stmmac_xgmac2_mdio_write()168 value |= (priv->clk_csr << priv->hw->mii.clk_csr_shift) in stmmac_mdio_read()224 value |= (priv->clk_csr << priv->hw->mii.clk_csr_shift) in stmmac_mdio_write()
63 plat->clk_csr = 2; /* clk_csr_i = 20-35MHz & MDC = clk_csr_i/16 */ in common_default_data()117 plat->clk_csr = 5; in intel_mgbe_common_data()383 plat->clk_csr = 5; in snps_gmac5_default_data()
242 if (!(priv->clk_csr & MAC_CSR_H_FRQ_MASK)) { in stmmac_clk_csr_set()244 priv->clk_csr = STMMAC_CSR_20_35M; in stmmac_clk_csr_set()246 priv->clk_csr = STMMAC_CSR_35_60M; in stmmac_clk_csr_set()248 priv->clk_csr = STMMAC_CSR_60_100M; in stmmac_clk_csr_set()250 priv->clk_csr = STMMAC_CSR_100_150M; in stmmac_clk_csr_set()252 priv->clk_csr = STMMAC_CSR_150_250M; in stmmac_clk_csr_set()254 priv->clk_csr = STMMAC_CSR_250_300M; in stmmac_clk_csr_set()259 priv->clk_csr = 0x03; in stmmac_clk_csr_set()261 priv->clk_csr = 0x02; in stmmac_clk_csr_set()263 priv->clk_csr = 0x01; in stmmac_clk_csr_set()[all …]
194 int clk_csr; member
444 plat->clk_csr = -1; in stmmac_probe_config_dt()445 of_property_read_u32(np, "clk_csr", &plat->clk_csr); in stmmac_probe_config_dt()
44 int clk_csr; member
140 int clk_csr; member
176 priv->clk_csr = SXGBE_CSR_100_150M; in sxgbe_clk_csr_set()178 priv->clk_csr = SXGBE_CSR_150_250M; in sxgbe_clk_csr_set()180 priv->clk_csr = SXGBE_CSR_250_300M; in sxgbe_clk_csr_set()182 priv->clk_csr = SXGBE_CSR_300_350M; in sxgbe_clk_csr_set()184 priv->clk_csr = SXGBE_CSR_350_400M; in sxgbe_clk_csr_set()186 priv->clk_csr = SXGBE_CSR_400_500M; in sxgbe_clk_csr_set()2155 if (!priv->plat->clk_csr) in sxgbe_drv_probe()2158 priv->clk_csr = priv->plat->clk_csr; in sxgbe_drv_probe()
48 ((sp->clk_csr & 0x7) << 19) | SXGBE_MII_BUSY; in sxgbe_mdio_ctrl_data()
489 int clk_csr; member
486 unsigned int clk_csr; in qat_hal_clr_reset() local502 clk_csr = GET_GLB_CSR(handle, ICP_GLOBAL_CLK_ENABLE); in qat_hal_clr_reset()503 clk_csr |= handle->hal_handle->ae_mask << 0; in qat_hal_clr_reset()504 clk_csr |= handle->hal_handle->slice_mask << 20; in qat_hal_clr_reset()505 SET_GLB_CSR(handle, ICP_GLOBAL_CLK_ENABLE, clk_csr); in qat_hal_clr_reset()
123 int clk_csr;159 o clk_csr: fixed CSR Clock range selection.
