| /Linux-v5.4/arch/arm/include/asm/hardware/ |
| D | cp14.h | 45 #define RCP14_DBGDIDR() MRC14(0, c0, c0, 0)
46 #define RCP14_DBGDSCRint() MRC14(0, c0, c1, 0)
47 #define RCP14_DBGDTRRXint() MRC14(0, c0, c5, 0)
48 #define RCP14_DBGWFAR() MRC14(0, c0, c6, 0)
49 #define RCP14_DBGVCR() MRC14(0, c0, c7, 0)
50 #define RCP14_DBGECR() MRC14(0, c0, c9, 0)
51 #define RCP14_DBGDSCCR() MRC14(0, c0, c10, 0)
52 #define RCP14_DBGDSMCR() MRC14(0, c0, c11, 0)
53 #define RCP14_DBGDTRRXext() MRC14(0, c0, c0, 2)
54 #define RCP14_DBGDSCRext() MRC14(0, c0, c2, 2)
[all …]
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| /Linux-v5.4/arch/arm/include/asm/ |
| D | kvm_hyp.h | 36 #define MIDR __ACCESS_CP15(c0, 0, c0, 0)
37 #define CSSELR __ACCESS_CP15(c0, 2, c0, 0)
38 #define VPIDR __ACCESS_CP15(c0, 4, c0, 0)
39 #define VMPIDR __ACCESS_CP15(c0, 4, c0, 5)
40 #define SCTLR __ACCESS_CP15(c1, 0, c0, 0)
41 #define CPACR __ACCESS_CP15(c1, 0, c0, 2)
46 #define TTBCR __ACCESS_CP15(c2, 0, c0, 2)
47 #define HTCR __ACCESS_CP15(c2, 4, c0, 2)
49 #define DACR __ACCESS_CP15(c3, 0, c0, 0)
50 #define DFSR __ACCESS_CP15(c5, 0, c0, 0)
[all …]
|
| D | tls.h | 14 mrc p15, 0, \tmp2, c13, c0, 2 @ get the user r/w register
15 mcr p15, 0, \tp, c13, c0, 3 @ set TLS register
16 mcr p15, 0, \tpuser, c13, c0, 2 @ and the user r/w register
26 mrcne p15, 0, \tmp2, c13, c0, 2 @ get the user r/w register
27 mcrne p15, 0, \tp, c13, c0, 3 @ yes, set TLS register
28 mcrne p15, 0, \tpuser, c13, c0, 2 @ set user r/w register
|
| /Linux-v5.4/arch/arm/mm/ |
| D | proc-v6.S | 39 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
42 mcr p15, 0, r0, c1, c0, 0 @ disable caches
57 mrc p15, 0, r1, c1, c0, 0 @ ctrl register
59 mcr p15, 0, r1, c1, c0, 0 @ disable MMU
76 mcr p15, 0, r1, c7, c0, 4 @ wait for interrupt
104 mcr p15, 0, r0, c2, c0, 0 @ set TTB 0
106 mrc p15, 0, r2, c13, c0, 1 @ read current context ID
111 mcr p15, 0, r1, c13, c0, 1 @ set context ID
139 mrc p15, 0, r4, c13, c0, 0 @ FCSE/PID
141 mrc p15, 0, r5, c3, c0, 0 @ Domain ID
[all …]
|
| D | proc-v7.S | 32 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
35 mcr p15, 0, r0, c1, c0, 0 @ disable caches
55 mrc p15, 0, r2, c1, c0, 0 @ ctrl register
58 mcr p15, 0, r2, c1, c0, 0 @ disable MMU
134 mrc p15, 0, r4, c13, c0, 0 @ FCSE/PID
135 mrc p15, 0, r5, c13, c0, 3 @ User r/o thread ID
138 mrc p15, 0, r6, c3, c0, 0 @ Domain ID
142 mrc p15, 0, r7, c2, c0, 1 @ TTB 1
144 mrc p15, 0, r11, c2, c0, 2 @ TTB control register
146 mrc p15, 0, r8, c1, c0, 0 @ Control register
[all …]
|
| D | proc-sa1100.S | 42 mcr p15, 0, r0, c9, c0, 5 @ Allow read-buffer operations from userland
54 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
57 mcr p15, 0, r0, c1, c0, 0 @ disable caches
78 mrc p15, 0, ip, c1, c0, 0 @ ctrl register
81 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
147 mcr p15, 0, ip, c9, c0, 0 @ invalidate RB
148 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
175 mrc p15, 0, r4, c3, c0, 0 @ domain ID
176 mrc p15, 0, r5, c13, c0, 0 @ PID
177 mrc p15, 0, r6, c1, c0, 0 @ control reg
[all …]
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| D | proc-arm740.S | 37 mrc p15, 0, r0, c1, c0, 0
40 mcr p15, 0, r0, c1, c0, 0 @ disable caches
51 mcr p15, 0, ip, c7, c0, 0 @ invalidate cache
52 mrc p15, 0, ip, c1, c0, 0 @ get ctrl register
54 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
62 mcr p15, 0, r0, c7, c0, 0 @ invalidate caches
71 mcr p15, 0, r0, c6, c0 @ set area 0, default
97 mcr p15, 0, r0, c2, c0 @ Region 1&2 cacheable
103 mcr p15, 0, r0, c3, c0
107 mcr p15, 0, r0, c5, c0 @ all read/write access
[all …]
|
| D | proc-xsc3.S | 56 mrc p15, 0, \rd, c2, c0, 0 @ arbitrary read of cp15
89 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
92 mcr p15, 0, r0, c1, c0, 0 @ disable caches
109 mrc p15, 0, r1, c1, c0, 0 @ ctrl register
112 mcr p15, 0, r1, c1, c0, 0 @ ctrl register
115 mcr p15, 0, r1, c1, c0, 0 @ ctrl register
137 mcr p14, 0, r0, c7, c0, 0 @ go to idle
366 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
416 mrc p14, 0, r4, c6, c0, 0 @ clock configuration, for turbo mode
418 mrc p15, 0, r6, c13, c0, 0 @ PID
[all …]
|
| D | proc-mohawk.S | 41 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
44 mcr p15, 0, r0, c1, c0, 0 @ disable caches
65 mrc p15, 0, ip, c1, c0, 0 @ ctrl register
68 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
82 mcr p15, 0, r0, c7, c0, 4 @ wait for interrupt
321 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
345 mrc p14, 0, r4, c6, c0, 0 @ clock configuration, for turbo mode
347 mrc p15, 0, r6, c13, c0, 0 @ PID
348 mrc p15, 0, r7, c3, c0, 0 @ domain ID
349 mrc p15, 0, r8, c1, c0, 1 @ auxiliary control reg
[all …]
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| D | proc-arm926.S | 50 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
53 mcr p15, 0, r0, c1, c0, 0 @ disable caches
74 mrc p15, 0, ip, c1, c0, 0 @ ctrl register
77 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
90 mrc p15, 0, r1, c1, c0, 0 @ Read control register
96 mcr p15, 0, r2, c1, c0, 0 @ Disable I cache
97 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
98 mcr p15, 0, r1, c1, c0, 0 @ Restore ICache enable
366 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
394 mrc p15, 0, r4, c13, c0, 0 @ PID
[all …]
|
| D | proc-arm940.S | 36 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
39 mcr p15, 0, r0, c1, c0, 0 @ disable caches
53 mrc p15, 0, ip, c1, c0, 0 @ ctrl register
56 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
66 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
292 mcr p15, 0, r0, c6, c0, 0 @ set area 0, default
293 mcr p15, 0, r0, c6, c0, 1
308 mcr p15, 0, r0, c2, c0, 0 @ Region 1&2 cacheable
309 mcr p15, 0, r0, c2, c0, 1
315 mcr p15, 0, r0, c3, c0, 0
[all …]
|
| D | proc-xscale.S | 69 mrc p15, 0, \rd, c2, c0, 0 @ arbitrary read of cp15
75 mrc p15, 0, \rd, c2, c0, 0 @ arbitrary read of cp15
116 mrc p15, 0, r1, c1, c0, 1
118 mcr p15, 0, r1, c1, c0, 1
125 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
128 mcr p15, 0, r0, c1, c0, 0 @ disable caches
149 mrc p15, 0, r1, c1, c0, 0 @ ctrl register
154 mcr p15, 0, r1, c1, c0, 0 @ ctrl register
157 mcr p15, 0, r1, c1, c0, 0 @ ctrl register
179 mcr p14, 0, r0, c7, c0, 0 @ Go to IDLE
[all …]
|
| D | proc-arm720.S | 43 mrc p15, 0, r0, c1, c0, 0
46 mcr p15, 0, r0, c1, c0, 0 @ disable caches
67 mcr p15, 0, r0, c2, c0, 0 @ update page table ptr
97 mrc p15, 0, ip, c1, c0, 0 @ get ctrl register
100 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
112 mrc p15, 0, r0, c1, c0 @ get control register
142 mrc p15, 0, r0, c1, c0 @ get control register
|
| /Linux-v5.4/arch/arm/include/debug/ |
| D | icedcc.S | 16 mcr p14, 0, \rd, c0, c5, 0
21 mrc p14, 0, \rx, c0, c1, 0
31 mrc p14, 0, \rx, c0, c1, 0
40 mcr p14, 0, \rd, c8, c0, 0
45 mrc p14, 0, \rx, c14, c0, 0
55 mrc p14, 0, \rx, c14, c0, 0
64 mcr p14, 0, \rd, c1, c0, 0
69 mrc p14, 0, \rx, c0, c0, 0
80 mrc p14, 0, \rx, c0, c0, 0
|
| D | exynos.S | 21 mrc p15, 0, \tmp, c0, c0, 0
25 mrc p15, 0, \tmp, c0, c0, 5
|
| /Linux-v5.4/drivers/gpu/drm/nouveau/nvkm/engine/sec/fuc/ |
| D | g98.fuc0s | 514 cxsin $c0
515 cxsout $c0
525 cxsin $c0
526 cenc $c0 $c0
527 cxsout $c0
533 cxsin $c0
534 cdec $c0 $c0
535 cxsout $c0
540 cxsin $c0
541 cxor $c6 $c0
[all …]
|
| /Linux-v5.4/arch/arm/mach-sunxi/ |
| D | headsmp.S | 25 mrc p15, 0, r1, c0, c0, 0
37 mrc p15, 1, r1, c15, c0, 4
39 mcr p15, 1, r1, c15, c0, 4
42 mrc p15, 1, r1, c15, c0, 0
47 mcr p15, 1, r1, c15, c0, 0
50 mrc p15, 1, r1, c9, c0, 2
53 mcr p15, 1, r1, c9, c0, 2
|
| /Linux-v5.4/arch/arm/mach-omap2/ |
| D | sleep44xx.S | 88 mrc p15, 0, r0, c1, c0, 0
90 mcr p15, 0, r0, c1, c0, 0
108 mrc p15, 0, r0, c0, c0, 5 @ Read MPIDR
119 mrc p15, 0, r0, c0, c0, 5 @ Read MPIDR
128 mrcne p15, 0, r0, c1, c0, 1
130 mcrne p15, 0, r0, c1, c0, 1
146 mrc p15, 0, r5, c0, c0, 5 @ Read MPIDR
189 mrc p15, 0, r0, c1, c0, 0
192 mcreq p15, 0, r0, c1, c0, 0
201 mrc p15, 0, r0, c1, c0, 1
[all …]
|
| D | omap-headsmp.S | 46 mrc p15, 0, r4, c0, c0, 5
64 mrc p15, 0, r4, c0, c0, 5
86 mrc p15, 0, r4, c0, c0, 5
103 mrc p15, 0, r4, c0, c0, 5
|
| /Linux-v5.4/arch/arm/mach-tegra/ |
| D | sleep.S | 38 mrc p15, 0, r2, c1, c0, 0
41 mcrne p15, 0, r2, c1, c0, 0
63 mrc p15, 0, r0, c0, c0, 5
68 mrc p15, 0x1, r0, c9, c0, 2
73 mcrne p15, 0x1, r0, c9, c0, 2
114 mrc p15, 0, r3, c1, c0, 0
118 mcr p15, 0, r3, c1, c0, 0
|
| D | sleep.h | 70 mrc p15, 0, \rd, c0, c0, 5
82 mrc p15, 0, \tmp1, c0, c0, 0
90 mrc p15, 0, \tmp1, c1, c0, 1 @ ACTLR
92 mcr p15, 0, \tmp1, c1, c0, 1 @ ACTLR
96 mrceq p15, 0, \tmp1, c0, c0, 5
|
| /Linux-v5.4/arch/arm/kvm/ |
| D | init.S | 62 mcr p15, 4, r1, c12, c0, 0 @ HVBAR
69 mrc p15, 4, r0, c2, c0, 2 @ HTCR
72 mrc p15, 0, r1, c2, c0, 2 @ TTBCR
75 mcr p15, 4, r0, c2, c0, 2 @ HTCR
96 mrc p15, 4, r0, c1, c0, 0 @ HSCR
99 mrc p15, 0, r1, c1, c0, 0 @ SCTLR
106 mcr p15, 4, r0, c1, c0, 0 @ HSCR
129 mrc p15, 4, r1, c1, c0, 0 @ HSCTLR
132 mcr p15, 4, r1, c1, c0, 0 @ HSCTLR
141 mcr p15, 4, r1, c12, c0, 0 @ HVBAR
|
| /Linux-v5.4/arch/arm/boot/compressed/ |
| D | head.S | 32 mcr p14, 0, \ch, c0, c5, 0
38 mcr p14, 0, \ch, c8, c0, 0
44 mcr p14, 0, \ch, c1, c0, 0
92 mrc p15, 0, r0, c1, c0
690 mcr p15, 0, r0, c2, c0, 0 @ D-cache on
691 mcr p15, 0, r0, c2, c0, 1 @ I-cache on
692 mcr p15, 0, r0, c3, c0, 0 @ write-buffer on
695 mcr p15, 0, r0, c5, c0, 1 @ I-access permission
696 mcr p15, 0, r0, c5, c0, 0 @ D-access permission
702 mrc p15, 0, r0, c1, c0, 0 @ read control reg
[all …]
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| /Linux-v5.4/arch/arm/kvm/hyp/ |
| D | hyp-entry.S | 18 mrc p15, 4, \reg, c13, c0, 2 @ HTPIDR
115 mcr p15, 4, r0, c0, c0, 0 /* VPIDR */
121 mrc p15, 4, r0, c0, c0, 0 /* VPIDR */
122 mrc p15, 0, r2, c0, c0, 0 /* MIDR */
123 mcr p15, 4, r2, c0, c0, 0 /* VPIDR */
|
| /Linux-v5.4/arch/arm/mach-spear/ |
| D | headsmp.S | 21 mrc p15, 0, r0, c0, c0, 5
32 mrc p15, 0, r0, c1, c0, 1
34 mcr p15, 0, r0, c1, c0, 1
|
