Lines Matching refs:c0
32 mcr p14, 0, \ch, c0, c5, 0
38 mcr p14, 0, \ch, c8, c0, 0
44 mcr p14, 0, \ch, c1, c0, 0
92 mrc p15, 0, r0, c1, c0
690 mcr p15, 0, r0, c2, c0, 0 @ D-cache on
691 mcr p15, 0, r0, c2, c0, 1 @ I-cache on
692 mcr p15, 0, r0, c3, c0, 0 @ write-buffer on
695 mcr p15, 0, r0, c5, c0, 1 @ I-access permission
696 mcr p15, 0, r0, c5, c0, 0 @ D-access permission
702 mrc p15, 0, r0, c1, c0, 0 @ read control reg
707 mcr p15, 0, r0, c1, c0, 0 @ write control reg
719 mcr p15, 0, r0, c2, c0, 0 @ cache on
720 mcr p15, 0, r0, c3, c0, 0 @ write-buffer on
723 mcr p15, 0, r0, c5, c0, 0 @ access permission
726 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
731 mrc p15, 0, r0, c1, c0, 0 @ read control reg
736 mcr p15, 0, r0, c1, c0, 0 @ write control reg
739 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
792 mrc p15, 0, r0, c1, c0, 0 @ read SCTLR
795 mcr p15, 0, r0, c1, c0, 0 @ write SCTLR
801 mcr p15, 7, r0, c15, c0, 0
812 mrc p15, 0, r0, c1, c0, 0 @ read control reg
825 mrc p15, 0, r11, c0, c1, 4 @ read ID_MMFR0
834 mrc p15, 0, r0, c1, c0, 0 @ read control reg
843 mrcne p15, 0, r6, c2, c0, 2 @ read ttb control reg
848 mcrne p15, 0, r3, c2, c0, 0 @ load page table pointer
849 mcrne p15, 0, r1, c3, c0, 0 @ load domain access control
850 mcrne p15, 0, r6, c2, c0, 2 @ load ttb control
853 mcr p15, 0, r0, c1, c0, 0 @ load control register
854 mrc p15, 0, r0, c1, c0, 0 @ and read it back
867 mrc p15, 0, r0, c1, c0, 0 @ read control reg
880 mcr p15, 0, r3, c2, c0, 0 @ load page table pointer
881 mcr p15, 0, r1, c3, c0, 0 @ load domain access control
884 1: mcr p15, 0, r0, c1, c0, 0 @ load control register
885 mrc p15, 0, r0, c1, c0, 0 @ and read it back to
907 mrc p15, 0, r9, c0, c0 @ get processor ID
1114 mrc p15, 0, r0, c1, c0
1116 mcr p15, 0, r0, c1, c0 @ turn MPU and cache off
1124 mrc p15, 0, r0, c1, c0
1126 mcr p15, 0, r0, c1, c0, 0 @ turn MPU and cache off
1128 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
1133 mrc p15, 0, r0, c1, c0
1135 mcr p15, 0, r0, c1, c0 @ turn MMU and cache off
1143 mrc p15, 0, r0, c1, c0
1149 mcr p15, 0, r0, c1, c0 @ turn MMU and cache off
1214 mrc p15, 0, r10, c0, c1, 5 @ read ID_MMFR1
1223 mrc p15, 1, r0, c0, c0, 1 @ read clidr
1234 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
1236 mrc p15, 1, r1, c0, c0, 0 @ read the new csidr
1265 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
1287 mrc p15, 0, r3, c0, c0, 1 @ read cache type
1321 mcr p15, 0, r1, c7, c0, 0 @ invalidate whole cache v3
1456 mrc p15, 0, r1, c1, c0, 0 @ read SCTLR
1460 mcr p15, 0, r1, c1, c0, 0 @ write SCTLR