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Searched refs:XAXIDMA_TX_CR_OFFSET (Results 1 – 3 of 3) sorted by relevance

/Linux-v5.4/drivers/net/ethernet/ni/
Dnixge.c26 #define XAXIDMA_TX_CR_OFFSET 0x00 /* Channel control */ macro
356 cr = nixge_dma_read_reg(priv, XAXIDMA_TX_CR_OFFSET); in nixge_hw_dma_bd_init()
366 nixge_dma_write_reg(priv, XAXIDMA_TX_CR_OFFSET, cr); in nixge_hw_dma_bd_init()
383 cr = nixge_dma_read_reg(priv, XAXIDMA_TX_CR_OFFSET); in nixge_hw_dma_bd_init()
384 nixge_dma_write_reg(priv, XAXIDMA_TX_CR_OFFSET, in nixge_hw_dma_bd_init()
415 __nixge_device_reset(priv, XAXIDMA_TX_CR_OFFSET); in nixge_device_reset()
721 cr = nixge_dma_read_reg(priv, XAXIDMA_TX_CR_OFFSET); in nixge_tx_irq()
725 nixge_dma_write_reg(priv, XAXIDMA_TX_CR_OFFSET, cr); in nixge_tx_irq()
770 cr = nixge_dma_read_reg(priv, XAXIDMA_TX_CR_OFFSET); in nixge_rx_irq()
774 nixge_dma_write_reg(priv, XAXIDMA_TX_CR_OFFSET, cr); in nixge_rx_irq()
[all …]
/Linux-v5.4/drivers/net/ethernet/xilinx/
Dxilinx_axienet_main.c255 cr = axienet_dma_in32(lp, XAXIDMA_TX_CR_OFFSET); in axienet_dma_bd_init()
265 axienet_dma_out32(lp, XAXIDMA_TX_CR_OFFSET, cr); in axienet_dma_bd_init()
282 cr = axienet_dma_in32(lp, XAXIDMA_TX_CR_OFFSET); in axienet_dma_bd_init()
283 axienet_dma_out32(lp, XAXIDMA_TX_CR_OFFSET, in axienet_dma_bd_init()
450 axienet_dma_out32(lp, XAXIDMA_TX_CR_OFFSET, XAXIDMA_CR_RESET_MASK); in __axienet_device_reset()
452 while (axienet_dma_in32(lp, XAXIDMA_TX_CR_OFFSET) & in __axienet_device_reset()
797 cr = axienet_dma_in32(lp, XAXIDMA_TX_CR_OFFSET); in axienet_tx_irq()
801 axienet_dma_out32(lp, XAXIDMA_TX_CR_OFFSET, cr); in axienet_tx_irq()
846 cr = axienet_dma_in32(lp, XAXIDMA_TX_CR_OFFSET); in axienet_rx_irq()
850 axienet_dma_out32(lp, XAXIDMA_TX_CR_OFFSET, cr); in axienet_rx_irq()
[all …]
Dxilinx_axienet.h74 #define XAXIDMA_TX_CR_OFFSET 0x00000000 /* Channel control */ macro