Searched refs:VTD_PAGE_SHIFT (Results 1 – 5 of 5) sorted by relevance
68 #define MAX_AGAW_PFN_WIDTH (MAX_AGAW_WIDTH - VTD_PAGE_SHIFT)70 #define __DOMAIN_MAX_PFN(gaw) ((((uint64_t)1) << (gaw-VTD_PAGE_SHIFT)) - 1)77 #define DOMAIN_MAX_ADDR(gaw) (((uint64_t)__DOMAIN_MAX_PFN(gaw)) << VTD_PAGE_SHIFT)155 return dma_pfn >> (PAGE_SHIFT - VTD_PAGE_SHIFT); in dma_to_mm_pfn()160 return mm_pfn << (PAGE_SHIFT - VTD_PAGE_SHIFT); in mm_to_dma_pfn()558 int addr_width = agaw_to_width(domain->agaw) - VTD_PAGE_SHIFT; in domain_pfn_supported()915 pteval = ((uint64_t)virt_to_dma_pfn(tmp_page) << VTD_PAGE_SHIFT) | DMA_PTE_READ | DMA_PTE_WRITE; in pfn_to_dma_pte()1428 !pci_enable_ats(pdev, VTD_PAGE_SHIFT)) { in iommu_enable_dev_iotlb()1492 uint64_t addr = (uint64_t)pfn << VTD_PAGE_SHIFT; in iommu_flush_iotlb_psi()2192 return PAGE_ALIGN(host_addr + size) >> VTD_PAGE_SHIFT; in aligned_nrpages()[all …]
144 unsigned long last = address + ((unsigned long)(pages - 1) << VTD_PAGE_SHIFT); in intel_flush_svm_range_dev()177 (end - start + PAGE_SIZE - 1) >> VTD_PAGE_SHIFT, 0); in intel_invalidate_range()561 address = (u64)req->addr << VTD_PAGE_SHIFT; in prq_event_thread()
441 qi_flush_dev_iotlb(iommu, sid, pfsid, qdep, 0, 64 - VTD_PAGE_SHIFT); in devtlb_invalidation_with_pasid()
1354 WARN_ON_ONCE(addr & ((1ULL << (VTD_PAGE_SHIFT + mask)) - 1)); in qi_flush_dev_iotlb()1355 addr |= (1ULL << (VTD_PAGE_SHIFT + mask - 1)) - 1; in qi_flush_dev_iotlb()
29 #define VTD_PAGE_SHIFT (12) macro30 #define VTD_PAGE_SIZE (1UL << VTD_PAGE_SHIFT)31 #define VTD_PAGE_MASK (((u64)-1) << VTD_PAGE_SHIFT)
