| /Linux-v5.4/drivers/gpu/drm/amd/display/dc/dce/ |
| D | dce_ipp.c | 104 REG_SET_3(CUR_COLOR1, 0, in dce_ipp_cursor_set_attributes()
109 REG_SET_3(CUR_COLOR2, 0, in dce_ipp_cursor_set_attributes()
189 REG_SET_3(DC_LUT_CONTROL, 0, in dce_ipp_program_input_lut()
228 REG_SET_3(DEGAMMA_CONTROL, 0, in dce_ipp_set_degamma()
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| D | dce_abm.c | 259 REG_SET_3(DC_ABM1_HG_MISC_CTRL, 0, in dce_abm_init()
264 REG_SET_3(DC_ABM1_IPCSC_COEFF_SEL, 0, in dce_abm_init()
282 REG_SET_3(DC_ABM1_HGLS_REG_READ_PROGRESS, 0, in dce_abm_init()
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| D | dce_link_encoder.c | 174 REG_SET_3(DP_DPHY_SYM0, 0, in program_pattern_symbols()
182 REG_SET_3(DP_DPHY_SYM1, 0, in program_pattern_symbols()
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| D | dce_i2c_hw.c | 124 REG_SET_3(DC_I2C_DATA, 0, in process_channel_reply()
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| D | dce_transform.c | 210 REG_SET_3(SCL_COEF_RAM_SELECT, 0, in program_multi_taps_filter()
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| /Linux-v5.4/drivers/gpu/drm/amd/display/dc/dcn20/ |
| D | dcn20_opp.c | 203 REG_SET_3(DPG_RAMP_CONTROL, 0, in opp2_set_disp_pattern_generator()
214 REG_SET_3(DPG_RAMP_CONTROL, 0, in opp2_set_disp_pattern_generator()
225 REG_SET_3(DPG_RAMP_CONTROL, 0, in opp2_set_disp_pattern_generator()
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| D | dcn20_optc.c | 142 REG_SET_3(OTG_VUPDATE_KEEPOUT, 0, in optc2_set_vupdate_keepout()
218 REG_SET_3(OPTC_DATA_SOURCE_SELECT, 0, in optc2_set_odm_bypass()
261 REG_SET_3(OPTC_DATA_SOURCE_SELECT, 0, in optc2_set_odm_combine()
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| D | dcn20_hubp.c | 149 REG_SET_3(DCN_SURF0_TTU_CNTL0, 0, in hubp2_program_deadline()
154 REG_SET_3(DCN_SURF1_TTU_CNTL0, 0, in hubp2_program_deadline()
159 REG_SET_3(DCN_CUR0_TTU_CNTL0, 0, in hubp2_program_deadline()
649 REG_SET_3(DMDATA_QOS_CNTL, 0, in hubp2_dmdata_set_attributes()
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| D | dcn20_dsc.c | 555 REG_SET_3(DSCC_PPS_CONFIG0, 0, in dsc_write_to_registers()
589 REG_SET_3(DSCC_PPS_CONFIG6, 0, in dsc_write_to_registers()
606 REG_SET_3(DSCC_PPS_CONFIG10, 0, in dsc_write_to_registers()
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| D | dcn20_dwb_scl.c | 701 REG_SET_3(WBSCL_COEF_RAM_SELECT, 0, in wbscl_set_scaler_filter()
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| /Linux-v5.4/drivers/gpu/drm/amd/display/dc/dcn10/ |
| D | dcn10_dpp_dscl.c | 271 REG_SET_3(SCL_COEF_RAM_TAP_SELECT, 0, in dpp1_dscl_set_scaler_filter()
553 REG_SET_3(DSCL_AUTOCAL, 0, in dpp1_dscl_set_scaler_auto_scale()
684 REG_SET_3(DSCL_AUTOCAL, 0, in dpp1_dscl_set_scaler_manual_scale()
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| D | dcn10_dpp.c | 322 REG_SET_3(FORMAT_CONTROL, 0, in dpp1_cnv_setup()
328 REG_SET_3(FORMAT_CONTROL, 0, in dpp1_cnv_setup()
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| D | dcn10_optc.c | 498 REG_SET_3(OTG_BLACK_COLOR, 0, in optc1_program_blank_color()
682 REG_SET_3(OTG_TRIGA_CNTL, 0, in optc1_enable_reset_trigger()
691 REG_SET_3(OTG_TRIGA_CNTL, 0, in optc1_enable_reset_trigger()
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| D | dcn10_hubp.c | 648 REG_SET_3(DCN_SURF0_TTU_CNTL0, 0, in hubp1_program_deadline()
653 REG_SET_3(DCN_SURF1_TTU_CNTL0, 0, in hubp1_program_deadline()
658 REG_SET_3(DCN_CUR0_TTU_CNTL0, 0, in hubp1_program_deadline()
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| D | dcn10_link_encoder.c | 146 REG_SET_3(DP_DPHY_SYM0, 0, in program_pattern_symbols()
154 REG_SET_3(DP_DPHY_SYM1, 0, in program_pattern_symbols()
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| D | dcn10_dpp_cm.c | 726 REG_SET_3(FORMAT_CONTROL, 0, in dpp1_full_bypass()
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| /Linux-v5.4/drivers/gpu/drm/amd/display/dc/inc/ |
| D | reg_helper.h | 72 #define REG_SET_3(reg, init_value, f1, v1, f2, v2, f3, v3) \ macro
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