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Searched refs:REG_GET (Results 1 – 25 of 64) sorted by relevance

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/Linux-v5.4/drivers/gpu/drm/amd/display/dc/dcn20/
Ddcn20_hubp.c673 REG_GET(DMDATA_STATUS, DMDATA_DONE, &status); in hubp2_dmdata_status_done()
859 REG_GET(DCSURF_FLIP_CONTROL2, SURFACE_TRIPLE_BUFFER_ENABLE, &triple_buffer_en); in hubp2_enable_triplebuffer()
873 REG_GET(DCSURF_FLIP_CONTROL2, SURFACE_TRIPLE_BUFFER_ENABLE, &triple_buffer_en); in hubp2_is_triplebuffer_enabled()
891 REG_GET(DCSURF_FLIP_CONTROL, in hubp2_is_flip_pending()
894 REG_GET(DCSURF_SURFACE_EARLIEST_INUSE, in hubp2_is_flip_pending()
897 REG_GET(DCSURF_SURFACE_EARLIEST_INUSE_HIGH, in hubp2_is_flip_pending()
1053 REG_GET(HUBPRET_CONTROL, in hubp2_read_state_common()
1066 REG_GET(BLANK_OFFSET_1, in hubp2_read_state_common()
1069 REG_GET(DST_DIMENSIONS, in hubp2_read_state_common()
1089 REG_GET(REF_FREQ_TO_PIX_FREQ, in hubp2_read_state_common()
[all …]
Ddcn20_stream_encoder.c351 REG_GET(DP_DSC_CNTL, DP_DSC_MODE, &s->dsc_mode); in enc2_read_state()
353 REG_GET(DP_DSC_CNTL, DP_DSC_SLICE_WIDTH, &s->dsc_slice_width); in enc2_read_state()
354 REG_GET(DP_SEC_CNTL6, DP_SEC_GSP7_LINE_NUM, &s->sec_gsp_pps_line_num); in enc2_read_state()
356 REG_GET(DP_MSA_VBID_MISC, DP_VBID6_LINE_REFERENCE, &s->vbid6_line_reference); in enc2_read_state()
357 REG_GET(DP_MSA_VBID_MISC, DP_VBID6_LINE_NUM, &s->vbid6_line_num); in enc2_read_state()
359 REG_GET(DP_SEC_CNTL, DP_SEC_GSP7_ENABLE, &s->sec_gsp_pps_enable); in enc2_read_state()
360 REG_GET(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, &s->sec_stream_enable); in enc2_read_state()
432 REG_GET(DP_SEC_METADATA_TRANSMISSION, in enc2_stream_encoder_update_dp_info_packets()
Ddcn20_link_encoder.c190 REG_GET(DP_DPHY_CNTL, DPHY_FEC_ACTIVE_STATUS, &active); in enc2_fec_is_active()
203 REG_GET(DP_DPHY_CNTL, DPHY_FEC_EN, &s->dphy_fec_en); in link_enc2_read_state()
204 REG_GET(DP_DPHY_CNTL, DPHY_FEC_READY_SHADOW, &s->dphy_fec_ready_shadow); in link_enc2_read_state()
205 REG_GET(DP_DPHY_CNTL, DPHY_FEC_ACTIVE_STATUS, &s->dphy_fec_active_status); in link_enc2_read_state()
Ddcn20_dwb.c177 REG_GET(CNV_UPDATE, CNV_UPDATE_LOCK, &pre_locked); in dwb2_update()
204 REG_GET(WB_ENABLE, WB_ENABLE, &wb_enabled); in dwb2_is_enabled()
205 REG_GET(CNV_MODE, CNV_FRAME_CAPTURE_EN, &cnv_frame_capture_en); in dwb2_is_enabled()
Ddcn20_vmid.c58 REG_GET(PAGE_TABLE_BASE_ADDR_LO32, in dcn20_wait_for_vmid_ready()
Ddcn20_dpp.c56 REG_GET(DPP_CONTROL, in dpp20_read_state()
58 REG_GET(CM_DGAM_CONTROL, in dpp20_read_state()
63 REG_GET(CM_GAMUT_REMAP_CONTROL, in dpp20_read_state()
/Linux-v5.4/drivers/gpu/drm/amd/display/dc/dcn10/
Ddcn10_mpc.c133 REG_GET(MPCC_TOP_SEL[mpcc_id], MPCC_TOP_SEL, &top_sel); in mpc1_is_mpcc_idle()
134 REG_GET(MPCC_OPP_ID[mpcc_id], MPCC_OPP_ID, &opp_id); in mpc1_is_mpcc_idle()
135 REG_GET(MPCC_STATUS[mpcc_id], MPCC_IDLE, &idle); in mpc1_is_mpcc_idle()
147 REG_GET(MPCC_TOP_SEL[mpcc_id], in mpc1_assert_mpcc_idle_before_connect()
372 REG_GET(MPCC_OPP_ID[mpcc_id], MPCC_OPP_ID, &opp_id); in mpc1_mpc_init_single_inst()
398 REG_GET(MUX[tree->opp_id], MPC_OUT_MUX, &out_mux); in mpc1_init_mpcc_list_from_hw()
402 REG_GET(MPCC_OPP_ID[mpcc_id], MPCC_OPP_ID, &opp_id); in mpc1_init_mpcc_list_from_hw()
403 REG_GET(MPCC_TOP_SEL[mpcc_id], MPCC_TOP_SEL, &top_sel); in mpc1_init_mpcc_list_from_hw()
404 REG_GET(MPCC_BOT_SEL[mpcc_id], MPCC_BOT_SEL, &bot_sel); in mpc1_init_mpcc_list_from_hw()
418 REG_GET(MPCC_OPP_ID[bot_mpcc_id], MPCC_OPP_ID, &opp_id); in mpc1_init_mpcc_list_from_hw()
[all …]
Ddcn10_hubp.c95 REG_GET(DCHUBP_CNTL, in hubp1_get_underflow_status()
727 REG_GET(DCSURF_FLIP_CONTROL, in hubp1_is_flip_pending()
730 REG_GET(DCSURF_SURFACE_EARLIEST_INUSE, in hubp1_is_flip_pending()
733 REG_GET(DCSURF_SURFACE_EARLIEST_INUSE_HIGH, in hubp1_is_flip_pending()
855 REG_GET(HUBPRET_CONTROL, in hubp1_read_state_common()
868 REG_GET(BLANK_OFFSET_1, in hubp1_read_state_common()
871 REG_GET(DST_DIMENSIONS, in hubp1_read_state_common()
891 REG_GET(REF_FREQ_TO_PIX_FREQ, in hubp1_read_state_common()
895 REG_GET(VBLANK_PARAMETERS_1, in hubp1_read_state_common()
898 REG_GET(VBLANK_PARAMETERS_3, in hubp1_read_state_common()
[all …]
Ddcn10_optc.c579 REG_GET(OTG_STATUS_FRAME_COUNT, in optc1_get_vblank_counter()
627 REG_GET(OTG_NOM_VERT_POSITION, in optc1_get_position()
651 REG_GET(OTG_FORCE_COUNT_NOW_CNTL, in optc1_did_triggered_reset_occur()
654 REG_GET(OTG_VERT_SYNC_CONTROL, in optc1_did_triggered_reset_occur()
678 REG_GET(OTG_V_SYNC_A_CNTL, in optc1_enable_reset_trigger()
1223 REG_GET(OTG_STEREO_STATUS, in optc1_is_stereo_left_eye()
1294 REG_GET(OTG_CONTROL, in optc1_read_otg_state()
1301 REG_GET(OTG_V_SYNC_A_CNTL, in optc1_read_otg_state()
1304 REG_GET(OTG_V_TOTAL, in optc1_read_otg_state()
1307 REG_GET(OTG_V_TOTAL_MAX, in optc1_read_otg_state()
[all …]
Ddcn10_dpp.c99 REG_GET(DPP_CONTROL, in dpp_read_state()
101 REG_GET(CM_IGAM_CONTROL, in dpp_read_state()
103 REG_GET(CM_IGAM_CONTROL, in dpp_read_state()
105 REG_GET(CM_DGAM_CONTROL, in dpp_read_state()
107 REG_GET(CM_RGAM_CONTROL, in dpp_read_state()
109 REG_GET(CM_GAMUT_REMAP_CONTROL, in dpp_read_state()
Ddcn10_link_encoder.c456 REG_GET(DIG_BE_CNTL, DIG_FE_SOURCE_SELECT, &value); in dcn10_get_dig_frontend()
541 REG_GET(DIG_BE_EN_CNTL, DIG_ENABLE, &value); in dcn10_is_dig_enabled()
1302 REG_GET(DP_MSE_SAT_UPDATE, in dcn10_link_encoder_update_mst_stream_allocation_table()
1305 REG_GET(DP_MSE_SAT_UPDATE, in dcn10_link_encoder_update_mst_stream_allocation_table()
1325 REG_GET(DIG_BE_CNTL, DIG_FE_SOURCE_SELECT, &field); in dcn10_link_encoder_connect_dig_be_to_fe()
1407 REG_GET(DIG_BE_CNTL, DIG_MODE, &value); in dcn10_get_dig_mode()
Ddcn10_dpp_cm.c224 REG_GET(CM_TEST_DEBUG_DATA, in dpp1_cm_program_color_matrix()
479 REG_GET(CM_TEST_DEBUG_DATA, in dpp1_program_input_csc()
656 REG_GET(CM_IGAM_LUT_RW_CONTROL, CM_IGAM_DGAM_CONFIG_STATUS, in dpp1_degamma_ram_inuse()
750 REG_GET(CM_IGAM_LUT_RW_CONTROL, CM_IGAM_DGAM_CONFIG_STATUS, in dpp1_ingamma_ram_inuse()
820 REG_GET(CM_IGAM_CONTROL, CM_IGAM_LUT_MODE, &ram_num); in dpp1_program_input_lut()
Ddcn10_hw_sequencer.c471 REG_GET(D1VGA_CONTROL, D1VGA_MODE_ENABLE, &in_vga1_mode); in dcn10_disable_vga()
472 REG_GET(D2VGA_CONTROL, D2VGA_MODE_ENABLE, &in_vga2_mode); in dcn10_disable_vga()
473 REG_GET(D3VGA_CONTROL, D3VGA_MODE_ENABLE, &in_vga3_mode); in dcn10_disable_vga()
474 REG_GET(D4VGA_CONTROL, D4VGA_MODE_ENABLE, &in_vga4_mode); in dcn10_disable_vga()
1750 REG_GET(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, in mmhub_read_vm_system_aperture_settings()
1752 REG_GET(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, in mmhub_read_vm_system_aperture_settings()
1755 REG_GET(MC_VM_SYSTEM_APERTURE_LOW_ADDR, in mmhub_read_vm_system_aperture_settings()
1758 REG_GET(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, in mmhub_read_vm_system_aperture_settings()
1776 REG_GET(DCHUBBUB_SDPIF_FB_BASE, SDPIF_FB_BASE, &fb_base_value); in mmhub_read_vm_context0_settings()
1777 REG_GET(DCHUBBUB_SDPIF_FB_OFFSET, SDPIF_FB_OFFSET, &fb_offset_value); in mmhub_read_vm_context0_settings()
[all …]
/Linux-v5.4/drivers/gpu/drm/amd/display/dc/dcn21/
Ddcn21_hubbub.c512 REG_GET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A, in hubbub21_wm_read_state()
515 REG_GET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A, in hubbub21_wm_read_state()
518 REG_GET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A, in hubbub21_wm_read_state()
521 REG_GET(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A, in hubbub21_wm_read_state()
526 REG_GET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B, in hubbub21_wm_read_state()
529 REG_GET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B, in hubbub21_wm_read_state()
532 REG_GET(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B, in hubbub21_wm_read_state()
535 REG_GET(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B, in hubbub21_wm_read_state()
540 REG_GET(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C, in hubbub21_wm_read_state()
543 REG_GET(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C, in hubbub21_wm_read_state()
[all …]
Ddcn21_hubp.c78 REG_GET(VBLANK_PARAMETERS_5, REFCYC_PER_VM_GROUP_VBLANK, &cur_value); in apply_DEDCN21_142_wa_for_hostvm_deadline()
83 REG_GET(VBLANK_PARAMETERS_6, in apply_DEDCN21_142_wa_for_hostvm_deadline()
90 REG_GET(FLIP_PARAMETERS_3, REFCYC_PER_VM_GROUP_FLIP, &cur_value); in apply_DEDCN21_142_wa_for_hostvm_deadline()
95 REG_GET(FLIP_PARAMETERS_4, REFCYC_PER_VM_REQ_FLIP, &cur_value); in apply_DEDCN21_142_wa_for_hostvm_deadline()
/Linux-v5.4/drivers/gpu/drm/amd/display/dc/dce/
Ddce_abm.c92 REG_GET(BL_PWM_PERIOD_CNTL, BL_PWM_PERIOD, &bl_period); in calculate_16_bit_backlight_from_pwm()
93 REG_GET(BL_PWM_PERIOD_CNTL, BL_PWM_PERIOD_BITCNT, &bl_int_count); in calculate_16_bit_backlight_from_pwm()
96 REG_GET(BL_PWM_CNTL, BL_ACTIVE_INT_FRAC_CNT, (uint32_t *)(&bl_pwm)); in calculate_16_bit_backlight_from_pwm()
97 REG_GET(BL_PWM_CNTL, BL_PWM_FRACTIONAL_EN, &fractional_duty_cycle_en); in calculate_16_bit_backlight_from_pwm()
347 REG_GET(LVTMA_PWRSEQ_REF_DIV, BL_PWM_REF_DIV, in dce_abm_immediate_disable()
361 REG_GET(BL_PWM_CNTL, BL_ACTIVE_INT_FRAC_CNT, &value); in dce_abm_init_backlight()
389 REG_GET(LVTMA_PWRSEQ_REF_DIV, BL_PWM_REF_DIV, in dce_abm_init_backlight()
Ddce_i2c_hw.c77 REG_GET(DC_I2C_SW_STATUS, DC_I2C_SW_STATUS, &i2c_sw_status); in get_channel_status()
108 REG_GET(SPEED, DC_I2C_DDC1_PRESCALE, &pre_scale); in get_speed()
138 REG_GET(DC_I2C_DATA, DC_I2C_DATA, &i2c_data); in process_channel_reply()
150 REG_GET(HW_STATUS, DC_I2C_DDC1_HW_STATUS, &i2c_hw_status); in is_engine_available()
154 REG_GET(DC_I2C_ARBITRATION, DC_I2C_REG_RW_CNTL_STATUS, &arbitrate); in is_engine_available()
165 REG_GET(DC_I2C_SW_STATUS, DC_I2C_SW_STATUS, &i2c_sw_status); in is_hw_busy()
359 REG_GET(DC_I2C_SW_STATUS, DC_I2C_SW_STATUS, &i2c_sw_status); in release_engine()
658 REG_GET(MICROSECOND_TIME_BASE_DIV, XTAL_REF_DIV, &xtal_ref_div); in dce100_i2c_hw_construct()
Ddce_aux.c268 *sw_status = REG_GET(AUX_SW_STATUS, AUX_SW_REPLY_BYTE_COUNT, in read_channel_reply()
284 REG_GET(AUX_SW_DATA, AUX_SW_DATA, &reply_result_32); in read_channel_reply()
302 REG_GET(AUX_SW_DATA, AUX_SW_DATA, &aux_sw_data_val); in read_channel_reply()
/Linux-v5.4/drivers/gpu/drm/amd/display/dc/gpio/
Dhw_gpio.c45 REG_GET(MASK_reg, MASK, &gpio->store.mask); in store_registers()
46 REG_GET(A_reg, A, &gpio->store.a); in store_registers()
47 REG_GET(EN_reg, EN, &gpio->store.en); in store_registers()
86 REG_GET(Y_reg, Y, value); in dal_hw_gpio_get_value()
Dhw_hpd.c94 REG_GET(int_status, in get_value()
/Linux-v5.4/drivers/video/fbdev/omap2/omapfb/dss/
Dhdmi4_core.c44 if (REG_GET(base, HDMI_CORE_DDC_STATUS, 4, 4) == 1) { in hdmi_core_ddc_init()
116 if (REG_GET(base, HDMI_CORE_DDC_STATUS, 6, 6) == 1) { in hdmi_core_ddc_edid()
121 if (REG_GET(base, HDMI_CORE_DDC_STATUS, 5, 5) == 1) { in hdmi_core_ddc_edid()
130 if (REG_GET(base, HDMI_CORE_DDC_STATUS, 4, 4) == 0) { in hdmi_core_ddc_edid()
137 while (REG_GET(base, HDMI_CORE_DDC_STATUS, 2, 2) == 1) { in hdmi_core_ddc_edid()
145 pedid[i] = REG_GET(base, HDMI_CORE_DDC_DATA, 7, 0); in hdmi_core_ddc_edid()
Dhdmi.h261 #define REG_GET(base, idx, start, end) \ macro
268 while (val != (v = REG_GET(base_addr, idx, b2, b1))) { in hdmi_wait_for_bit_change()
/Linux-v5.4/drivers/gpu/drm/omapdrm/dss/
Dhdmi4_core.c43 if (REG_GET(base, HDMI_CORE_DDC_STATUS, 4, 4) == 1) { in hdmi_core_ddc_init()
115 if (REG_GET(base, HDMI_CORE_DDC_STATUS, 6, 6) == 1) { in hdmi_core_ddc_edid()
120 if (REG_GET(base, HDMI_CORE_DDC_STATUS, 5, 5) == 1) { in hdmi_core_ddc_edid()
129 if (REG_GET(base, HDMI_CORE_DDC_STATUS, 4, 4) == 0) { in hdmi_core_ddc_edid()
136 while (REG_GET(base, HDMI_CORE_DDC_STATUS, 2, 2) == 1) { in hdmi_core_ddc_edid()
144 pedid[i] = REG_GET(base, HDMI_CORE_DDC_DATA, 7, 0); in hdmi_core_ddc_edid()
Dhdmi.h279 #define REG_GET(base, idx, start, end) \ macro
286 while (val != (v = REG_GET(base_addr, idx, b2, b1))) { in hdmi_wait_for_bit_change()
/Linux-v5.4/drivers/gpu/drm/amd/display/dc/bios/
Dbios_parser_helper.c61 REG_GET(BIOS_SCRATCH_6, S6_ACC_MODE, &acc_mode); in bios_is_accelerated_mode()

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