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Searched refs:PLLU_BASE (Results 1 – 5 of 5) sorted by relevance

/Linux-v5.4/drivers/clk/tegra/
Dclk-tegra210.c72 #define PLLU_BASE 0xc0 macro
2225 .base_reg = PLLU_BASE,
2846 reg = readl_relaxed(clk_base + PLLU_BASE); in tegra210_enable_pllu()
2851 writel(reg, clk_base + PLLU_BASE); in tegra210_enable_pllu()
2854 writel(reg, clk_base + PLLU_BASE); in tegra210_enable_pllu()
2856 readl_relaxed_poll_timeout_atomic(clk_base + PLLU_BASE, reg, in tegra210_enable_pllu()
2873 reg = readl_relaxed(clk_base + PLLU_BASE); in tegra210_init_pllu()
2883 reg = readl_relaxed(clk_base + PLLU_BASE); in tegra210_init_pllu()
2885 writel(reg, clk_base + PLLU_BASE); in tegra210_init_pllu()
2905 reg = readl_relaxed(clk_base + PLLU_BASE); in tegra210_init_pllu()
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Dclk-tegra114.c73 #define PLLU_BASE 0xc0 macro
472 .base_reg = PLLU_BASE,
970 CLK_SET_RATE_PARENT, clk_base + PLLU_BASE, in tegra114_pll_init()
Dclk-tegra124.c51 #define PLLU_BASE 0xc0 macro
717 .base_reg = PLLU_BASE,
1108 CLK_SET_RATE_PARENT, clk_base + PLLU_BASE, in tegra124_pll_init()
Dclk-tegra20.c52 #define PLLU_BASE 0xc0 macro
372 .base_reg = PLLU_BASE,
Dclk-tegra30.c71 #define PLLU_BASE 0xc0 macro
477 .base_reg = PLLU_BASE,