Lines Matching refs:PLLU_BASE
72 #define PLLU_BASE 0xc0 macro
2225 .base_reg = PLLU_BASE,
2846 reg = readl_relaxed(clk_base + PLLU_BASE); in tegra210_enable_pllu()
2851 writel(reg, clk_base + PLLU_BASE); in tegra210_enable_pllu()
2854 writel(reg, clk_base + PLLU_BASE); in tegra210_enable_pllu()
2856 readl_relaxed_poll_timeout_atomic(clk_base + PLLU_BASE, reg, in tegra210_enable_pllu()
2873 reg = readl_relaxed(clk_base + PLLU_BASE); in tegra210_init_pllu()
2883 reg = readl_relaxed(clk_base + PLLU_BASE); in tegra210_init_pllu()
2885 writel(reg, clk_base + PLLU_BASE); in tegra210_init_pllu()
2905 reg = readl_relaxed(clk_base + PLLU_BASE); in tegra210_init_pllu()
2907 writel_relaxed(reg, clk_base + PLLU_BASE); in tegra210_init_pllu()
3123 clk_base + PLLU_BASE, 16, 4, 0, in tegra210_pll_init()
3152 CLK_SET_RATE_PARENT, clk_base + PLLU_BASE, in tegra210_pll_init()
3159 CLK_SET_RATE_PARENT, clk_base + PLLU_BASE, in tegra210_pll_init()
3166 CLK_SET_RATE_PARENT, clk_base + PLLU_BASE, in tegra210_pll_init()