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Searched refs:PIPE_B (Results 1 – 25 of 27) sorted by relevance

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/Linux-v5.4/drivers/gpu/drm/i915/gvt/
Dhandlers.c1960 MMIO_D(PIPEDSL(PIPE_B), D_ALL); in init_generic_mmio_info()
1965 MMIO_DH(PIPECONF(PIPE_B), D_ALL, NULL, pipeconf_mmio_write); in init_generic_mmio_info()
1970 MMIO_D(PIPESTAT(PIPE_B), D_ALL); in init_generic_mmio_info()
1975 MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_B), D_ALL); in init_generic_mmio_info()
1980 MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_B), D_ALL); in init_generic_mmio_info()
1985 MMIO_D(CURCNTR(PIPE_B), D_ALL); in init_generic_mmio_info()
1989 MMIO_D(CURPOS(PIPE_B), D_ALL); in init_generic_mmio_info()
1993 MMIO_D(CURBASE(PIPE_B), D_ALL); in init_generic_mmio_info()
1997 MMIO_D(CUR_FBC_CTL(PIPE_B), D_ALL); in init_generic_mmio_info()
2020 MMIO_D(DSPCNTR(PIPE_B), D_ALL); in init_generic_mmio_info()
[all …]
Dreg.h74 (((p) == PIPE_B) ? (((q) == PLANE_PRIMARY) ? (_MMIO(0x50088)) : \
83 (((reg) == 0x50088 || (reg) == 0x50098) ? (PIPE_B) : \
Ddisplay.c49 pipe = PIPE_B; in get_edp_pipe()
396 [PIPE_B] = PIPE_B_VBLANK, in emulate_vblank_on_pipe()
Dcmd_parser.c1217 [1] = {PIPE_B, PLANE_A, PRIMARY_B_FLIP_DONE}, in gen8_decode_mi_display_flip()
1219 [3] = {PIPE_B, PLANE_B, SPRITE_B_FLIP_DONE}, in gen8_decode_mi_display_flip()
1275 info->pipe = PIPE_B; in skl_decode_mi_display_flip()
1289 info->pipe = PIPE_B; in skl_decode_mi_display_flip()
Dinterrupt.c450 DEFINE_GVT_GEN8_INTEL_GVT_IRQ_INFO(de_pipe_b, GEN8_DE_PIPE_ISR(PIPE_B));
/Linux-v5.4/drivers/gpu/drm/i915/
Di915_reg.h7956 #define ICL_DSC0_RC_RANGE_PARAMETERS_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
7959 #define ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
7962 #define ICL_DSC1_RC_RANGE_PARAMETERS_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
7965 #define ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
7984 #define ICL_DSC0_RC_RANGE_PARAMETERS_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
7987 #define ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
7990 #define ICL_DSC1_RC_RANGE_PARAMETERS_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
7993 #define ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
8009 #define ICL_DSC0_RC_RANGE_PARAMETERS_2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
8012 #define ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
[all …]
Di915_trace.h45 __entry->frame[PIPE_B], __entry->scanline[PIPE_B],
72 __entry->frame[PIPE_B], __entry->scanline[PIPE_B],
169 __entry->frame[PIPE_B], __entry->scanline[PIPE_B],
Dintel_pm.c509 case PIPE_B: in vlv_get_fifo_size()
959 FW_WM(wm->pipe[PIPE_B].plane[PLANE_CURSOR], CURSORB) | in g4x_write_wm_values()
960 FW_WM(wm->pipe[PIPE_B].plane[PLANE_PRIMARY], PLANEB) | in g4x_write_wm_values()
966 FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE0], SPRITEB) | in g4x_write_wm_values()
1009 FW_WM(wm->pipe[PIPE_B].plane[PLANE_CURSOR], CURSORB) | in vlv_write_wm_values()
1010 FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_PRIMARY], PLANEB) | in vlv_write_wm_values()
1021 FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_SPRITE1], SPRITED) | in vlv_write_wm_values()
1022 FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_SPRITE0], SPRITEC)); in vlv_write_wm_values()
1034 FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE1] >> 8, SPRITED_HI) | in vlv_write_wm_values()
1035 FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE0] >> 8, SPRITEC_HI) | in vlv_write_wm_values()
[all …]
Di915_pci.c104 [PIPE_B] = CURSOR_B_OFFSET, \
110 [PIPE_B] = CURSOR_B_OFFSET, \
117 [PIPE_B] = IVB_CURSOR_B_OFFSET, \
Dintel_device_info.c870 runtime->num_scalers[PIPE_B] = 2; in intel_device_info_runtime_init()
893 runtime->num_sprites[PIPE_B] = 2; in intel_device_info_runtime_init()
938 enabled_mask &= ~BIT(PIPE_B); in intel_device_info_runtime_init()
Di915_irq.c699 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_LEGACY_BLC_EVENT_STATUS); in i915_enable_asle_pipestat()
1747 case PIPE_B: in i9xx_pipestat_irq_ack()
2182 intel_pch_fifo_underrun_irq_handler(dev_priv, PIPE_B); in ibx_irq_handler()
3932 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS); in i8xx_irq_postinstall()
4106 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS); in i915_irq_postinstall()
4224 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS); in i965_irq_postinstall()
/Linux-v5.4/drivers/gpu/drm/i915/display/
Dintel_dpio_phy.c797 if (ch == DPIO_CH0 && pipe == PIPE_B) in chv_phy_pre_pll_enable()
809 if (pipe != PIPE_B) { in chv_phy_pre_pll_enable()
830 if (pipe != PIPE_B) in chv_phy_pre_pll_enable()
839 if (pipe != PIPE_B) in chv_phy_pre_pll_enable()
852 if (pipe != PIPE_B) in chv_phy_pre_pll_enable()
962 if (pipe != PIPE_B) { in chv_phy_post_pll_disable()
Dintel_pipe_crc.c182 case PIPE_B: in vlv_pipe_crc_ctl_reg()
246 case PIPE_B: in vlv_undo_pipe_scramble_reset()
Dintel_display_power.c1029 if ((I915_READ(PIPECONF(PIPE_B)) & PIPECONF_ENABLE) == 0) in i830_pipes_power_well_enable()
1030 i830_enable_pipe(dev_priv, PIPE_B); in i830_pipes_power_well_enable()
1036 i830_disable_pipe(dev_priv, PIPE_B); in i830_pipes_power_well_disable()
1044 I915_READ(PIPECONF(PIPE_B)) & PIPECONF_ENABLE; in i830_pipes_power_well_enabled()
1341 (I915_READ(DPLL(PIPE_B)) & DPLL_VCO_ENABLE) == 0) in assert_chv_phy_status()
1465 assert_pll_disabled(dev_priv, PIPE_B); in chv_dpio_cmn_power_well_disable()
2750 .hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
2951 .hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
3033 .hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
3093 .hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
[all …]
Dintel_display.h83 PIPE_B, enumerator
101 TRANSCODER_B = PIPE_B,
Dvlv_dsi.c992 enabled = I915_READ(PIPECONF(PIPE_B)) & PIPECONF_ENABLE; in intel_dsi_get_hw_state()
1016 *pipe = port == PORT_A ? PIPE_A : PIPE_B; in intel_dsi_get_hw_state()
1873 intel_encoder->crtc_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C); in vlv_dsi_init()
1877 intel_encoder->crtc_mask = BIT(PIPE_B); in vlv_dsi_init()
Dicl_dsi.c742 case PIPE_B: in gen11_dsi_configure_transcoder()
1323 *pipe = PIPE_B; in gen11_dsi_get_hw_state()
1587 encoder->crtc_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C); in icl_dsi_init()
Dintel_display_types.h1332 case PIPE_B: in vlv_pipe_to_channel()
Dintel_display.c1327 I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && !state && port_pipe == PIPE_B, in assert_pch_dp_disabled()
1345 I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && !state && port_pipe == PIPE_B, in assert_pch_hdmi_disabled()
1460 I915_WRITE(DPLL_MD(PIPE_B), pipe_config->dpll_hw_state.dpll_md); in chv_enable_pll()
1468 WARN_ON((I915_READ(DPLL(PIPE_B)) & DPLL_VGA_MODE_DIS) == 0); in chv_enable_pll()
5139 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE); in cpt_set_fdi_bc_bifurcation()
5159 case PIPE_B: in ivybridge_update_fdi_bc_bifurcation()
6869 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) { in valleyview_crtc_enable()
7214 case PIPE_B: in ironlake_check_fdi_lanes()
7237 other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_B); in ironlake_check_fdi_lanes()
7767 if (pipe == PIPE_B) in vlv_prepare_pll()
[all …]
Dintel_dp.c799 unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B); in vlv_find_free_pps()
928 for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) { in vlv_initial_pps_pipe()
3494 if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B)) in vlv_detach_power_sequencer()
4097 if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B && port != PORT_A) { in intel_dp_link_down()
7080 if (pipe != PIPE_A && pipe != PIPE_B) in intel_edp_init_connector()
7083 if (pipe != PIPE_A && pipe != PIPE_B) in intel_edp_init_connector()
Dintel_panel.c572 if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B)) in _vlv_get_backlight()
1734 if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B)) in vlv_setup_backlight()
Dintel_sprite.c966 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) in vlv_update_plane()
2598 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) { in intel_sprite_plane_create()
Dintel_ddi.c1815 case PIPE_B: in intel_ddi_enable_transcoder_func()
2004 *pipe_mask = BIT(PIPE_B); in intel_ddi_get_encoder_pipes()
/Linux-v5.4/drivers/video/fbdev/intelfb/
Dintelfbhw.h183 #define PIPE_B 1 macro
Dintelfbhw.c1059 if (pipe == PIPE_B) { in intelfbhw_mode_to_hw()
1302 if (dinfo->pipe == PIPE_B) { in intelfbhw_program_mode()

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