Lines Matching refs:PIPE_B
1327 I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && !state && port_pipe == PIPE_B, in assert_pch_dp_disabled()
1345 I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && !state && port_pipe == PIPE_B, in assert_pch_hdmi_disabled()
1460 I915_WRITE(DPLL_MD(PIPE_B), pipe_config->dpll_hw_state.dpll_md); in chv_enable_pll()
1468 WARN_ON((I915_READ(DPLL(PIPE_B)) & DPLL_VGA_MODE_DIS) == 0); in chv_enable_pll()
5139 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE); in cpt_set_fdi_bc_bifurcation()
5159 case PIPE_B: in ivybridge_update_fdi_bc_bifurcation()
6869 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) { in valleyview_crtc_enable()
7214 case PIPE_B: in ironlake_check_fdi_lanes()
7237 other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_B); in ironlake_check_fdi_lanes()
7767 if (pipe == PIPE_B) in vlv_prepare_pll()
8177 (pipe == PIPE_B || pipe == PIPE_C)) in intel_set_pipe_timings()
8550 if (crtc->pipe != PIPE_B) in i9xx_get_pfit_config()
8630 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B && in i9xx_get_initial_plane_config()
10262 trans_pipe = PIPE_B; in hsw_get_transcoder_state()
14922 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) { in intel_primary_plane_create()
16366 WARN_ON(I915_READ(CURCNTR(PIPE_B)) & MCURSOR_MODE); in i830_disable_pipe()