Searched refs:NUM_UCLK_DPM_LEVELS (Results 1 – 12 of 12) sorted by relevance
41 #define NUM_UCLK_DPM_LEVELS 4 macro50 #define MAX_UCLK_DPM_LEVEL (NUM_UCLK_DPM_LEVELS - 1)220 uint8_t MemVid[NUM_UCLK_DPM_LEVELS]; /* VID */221 PllSetting_t UclkLevel[NUM_UCLK_DPM_LEVELS]; /* Full PLL settings */222 uint8_t MemSocVoltageIndex[NUM_UCLK_DPM_LEVELS];
45 #define NUM_UCLK_DPM_LEVELS 4 macro60 #define MAX_UCLK_DPM_LEVEL (NUM_UCLK_DPM_LEVELS - 1)588 uint16_t FreqTableUclk [NUM_UCLK_DPM_LEVELS ]; // In MHz598 …uint8_t FreqTableUclkDiv [NUM_UCLK_DPM_LEVELS ]; // 0:Div-1, 1:Div-1/2, 2:Div-1/4, …603 uint16_t MemVddciVoltage [NUM_UCLK_DPM_LEVELS]; // mV(Q2)604 uint16_t MemMvddVoltage [NUM_UCLK_DPM_LEVELS]; // mV(Q2)
39 #define NUM_UCLK_DPM_LEVELS 4 macro49 #define MAX_UCLK_DPM_LEVEL (NUM_UCLK_DPM_LEVELS - 1)503 uint16_t FreqTableUclk [NUM_UCLK_DPM_LEVELS ]; // In MHz
42 #define NUM_UCLK_DPM_LEVELS 4 macro57 #define MAX_UCLK_DPM_LEVEL (NUM_UCLK_DPM_LEVELS - 1)424 uint16_t FreqTableUclk [NUM_UCLK_DPM_LEVELS ];
40 #define NUM_UCLK_DPM_LEVELS 4 macro53 #define MAX_UCLK_DPM_LEVEL (NUM_UCLK_DPM_LEVELS - 1)312 uint16_t FreqTableUclk [NUM_UCLK_DPM_LEVELS ];
333 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
1830 while (i < NUM_UCLK_DPM_LEVELS) { in vega10_populate_all_memory_levels()3484 return vdd_dep_table_on_mclk->entries[NUM_UCLK_DPM_LEVELS - 1].vddInd + 1; in vega10_get_soc_index_for_max_uclk()3508 if (data->smc_state_table.mem_boot_level == NUM_UCLK_DPM_LEVELS - 1) { in vega10_upload_dpm_bootup_level()
2341 PP_ASSERT_WITH_CODE(dpm_table->count <= NUM_UCLK_DPM_LEVELS, in vega12_set_uclk_to_highest_dpm_level()
3487 PP_ASSERT_WITH_CODE(dpm_table->count <= NUM_UCLK_DPM_LEVELS, in vega20_set_uclk_to_highest_dpm_level()
598 dpm_context->dpm_tables.uclk_table.max = driver_ppt->FreqTableUclk[NUM_UCLK_DPM_LEVELS - 1]; in navi10_set_default_dpm_table()
1648 for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++) in arcturus_dump_pptable()
2041 if (dpm_table->count > NUM_UCLK_DPM_LEVELS) { in vega20_set_uclk_to_highest_dpm_level()
