| /Linux-v5.4/Documentation/trace/ |
| D | events-msr.rst | 2 MSR Trace Events
5 The x86 kernel supports tracing most MSR (Model Specific Register) accesses.
13 Trace MSR reads:
17 - msr: MSR number
22 Trace MSR writes:
26 - msr: MSR number
39 to add symbolic MSR names.
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| /Linux-v5.4/Documentation/hwmon/ |
| D | fam15h_power.rst | 81 MaxCpuSwPwrAcc MSR C001007b
85 CpuSwPwrAcc MSR C001007a
88 by CU_PTSC MSR C0010280
98 MSR MaxCpuSwPwrAcc.
102 iii. At time x, SW reads CpuSwPwrAcc MSR and samples the PTSC.
106 iv. At time y, SW reads CpuSwPwrAcc MSR and samples the PTSC.
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| /Linux-v5.4/Documentation/virt/kvm/ |
| D | msr.txt | 11 Custom MSR list
14 The current supported Custom MSR list is:
29 guaranteed to update this data at the moment of MSR write.
31 to write more than once to this MSR. Fields have the following meanings:
45 particular MSR is global.
47 Availability of this MSR must be checked via bit 3 in 0x4000001 cpuid
125 Availability of this MSR must be checked via bit 3 in 0x4000001 cpuid
133 This MSR falls outside the reserved KVM range and may be removed in the
136 Availability of this MSR must be checked via bit 0 in 0x4000001 cpuid
143 This MSR falls outside the reserved KVM range and may be removed in the
[all …]
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| D | ppc-pv.txt | 115 MSR bits
118 The MSR contains bits that require hypervisor intervention and bits that do
127 If any other bit changes in the MSR, please still use mtmsr(d).
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| D | amd-memory-encryption.rst | 25 If support for SEV is present, MSR 0xc001_0010 (MSR_K8_SYSCFG) and MSR 0xc001_0015
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| /Linux-v5.4/drivers/net/hamradio/ |
| D | baycom_ser_hdx.c | 86 #define MSR(iobase) (iobase+6) macro
209 cur_s = inb(MSR(dev->base_addr)) & 0x10; /* the CTS line */ in ser12_rx()
346 hdlcdrv_setdcd(&bc->hdrv, !((inb(MSR(dev->base_addr)) ^ bc->opt_dcd) & 0x80)); in ser12_rx()
398 inb(MSR(dev->base_addr)); in ser12_interrupt()
432 b2 = inb(MSR(iobase)); in ser12_check_uart()
434 b3 = inb(MSR(iobase)) & 0xf0; in ser12_check_uart()
436 outb(b2, MSR(iobase)); in ser12_check_uart()
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| D | baycom_ser_fdx.c | 100 #define MSR(iobase) (iobase+6) macro
262 msr = inb(MSR(dev->base_addr)); in ser12_interrupt()
296 msr = inb(MSR(dev->base_addr)); in ser12_interrupt()
350 b2 = inb(MSR(iobase)); in ser12_check_uart()
352 b3 = inb(MSR(iobase)) & 0xf0; in ser12_check_uart()
354 outb(b2, MSR(iobase)); in ser12_check_uart()
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| D | yam.c | 157 #define MSR(iobase) (iobase+6) macro
300 inb(MSR(iobase)); in fpga_reset()
447 rc = inb(MSR(iobase)); /* check DONE signal */ in fpga_download()
476 inb(MSR(dev->base_addr)); in yam_set_uart()
503 b2 = inb(MSR(iobase)); in yam_check_uart()
505 b3 = inb(MSR(iobase)) & 0xf0; in yam_check_uart()
507 outb(b2, MSR(iobase)); in yam_check_uart()
745 unsigned char msr = inb(MSR(dev->base_addr)); in yam_interrupt()
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| /Linux-v5.4/arch/sparc/include/asm/ |
| D | floppy_64.h | 443 #define MSR (port + 4) macro
452 while (!((status = inb(MSR)) & 0x80) && --timeout) in sun_pci_fd_out_byte()
467 while (!((status = inb(MSR)) & 0x80) && --timeout) in sun_pci_fd_sensei()
488 outb(0x80, MSR); in sun_pci_fd_reset()
526 #undef MSR
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| /Linux-v5.4/Documentation/x86/ |
| D | pat.rst | 211 configurations. The PAT MSR must be updated by Linux in order to support WC
212 and WT attributes. Otherwise, the PAT MSR has the value programmed in it
213 by the firmware. Note, Xen enables WC attribute in the PAT MSR for guests.
216 MTRR PAT Call Sequence PAT State PAT MSR
239 OS PAT initializes PAT MSR with OS setting
240 BIOS PAT keeps PAT MSR with BIOS setting
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| D | tsx_async_abort.rst | 24 a) TSX disable - one of the mitigations is to disable TSX. A new MSR
109 There are two control bits in IA32_TSX_CTRL MSR:
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| D | amd-memory-encryption.rst | 56 If support for SME is present, MSR 0xc00100010 (MSR_K8_SYSCFG) can be used to
63 If SEV is supported, MSR 0xc0010131 (MSR_AMD64_SEV) can be used to determine if
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| /Linux-v5.4/drivers/powercap/ |
| D | Kconfig | 23 tristate "Intel RAPL Support via MSR Interface"
28 technology via MSR interface, which allows power limits to be enforced
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| /Linux-v5.4/drivers/staging/rtl8712/ |
| D | rtl8712_cmdctrl_regdef.h | 14 #define MSR (RTL8712_CMDCTRL_ + 0x000C) macro
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| /Linux-v5.4/Documentation/admin-guide/hw-vuln/ |
| D | tsx_async_abort.rst | 15 is 0 in the IA32_ARCH_CAPABILITIES MSR. On processors where the MDS_NO bit
16 (bit 5) is 0 in the IA32_ARCH_CAPABILITIES MSR, the existing MDS mitigations
191 and which get the new IA32_TSX_CTRL MSR through a microcode
192 update. This new MSR allows for the reliable deactivation of
219 provides a TSX control MSR. If so,
231 combinations of CPUID bit MD_CLEAR and IA32_ARCH_CAPABILITIES MSR bits MDS_NO
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| D | multihit.rst | 23 IA32_ARCH_CAPABILITIES MSR.
94 IA32_ARCH_CAPABILITIES MSR Not present Possibly vulnerable,check model
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| /Linux-v5.4/arch/powerpc/kernel/ |
| D | swsusp_asm64.S | 114 SAVE_SPECIAL(MSR)
244 RESTORE_SPECIAL(MSR)
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| /Linux-v5.4/drivers/usb/serial/ |
| D | io_16654.h | 38 #define MSR 6 // Modem Status Register macro
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| /Linux-v5.4/arch/x86/boot/ |
| D | early_serial_console.c | 20 #define MSR 6 /* Modem Status */ macro
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| /Linux-v5.4/Documentation/powerpc/ |
| D | transactional_memory.rst | 108 delivered. For future compatibility the MSR.TS field should be checked to
112 For 64-bit processes, uc->uc_mcontext.regs->msr is a full 64-bit MSR and its TS
115 For 32-bit processes, the mcontext's MSR register is only 32 bits; the top 32
116 bits are stored in the MSR of the second ucontext, i.e. in
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| D | ultravisor.rst | 55 * There is a new bit in the MSR that determines whether the current
56 process is running in secure mode, MSR(S) bit 41. MSR(S)=1, process
57 is in secure mode, MSR(s)=0 process is in normal mode.
59 * The MSR(S) bit can only be set by the Ultravisor.
61 * HRFID cannot be used to set the MSR(S) bit. If the hypervisor needs
68 * The privilege of a process is now determined by three MSR bits,
69 MSR(S, HV, PR). In each of the tables below the modes are listed
73 **Secure Mode MSR Settings**
87 **Normal Mode MSR Settings**
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| /Linux-v5.4/arch/x86/kernel/ |
| D | verify_cpu.S | 96 jnc .Lverify_cpu_check # only write MSR if bit was changed
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| /Linux-v5.4/drivers/staging/rtl8192u/ |
| D | r8192U_hw.h | 161 MSR = 0x303, // Media Status register enumerator
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| /Linux-v5.4/drivers/staging/rtl8188eu/hal/ |
| D | usb_halinit.c | 1138 val8 = usb_read8(Adapter, MSR) & 0x0c; in hw_var_set_opmode()
1140 usb_write8(Adapter, MSR, val8); in hw_var_set_opmode()
1231 val8 = usb_read8(Adapter, MSR) & 0x0c; in rtw_hal_set_hwreg()
1233 usb_write8(Adapter, MSR, val8); in rtw_hal_set_hwreg()
1240 val8 = usb_read8(Adapter, MSR) & 0x03; in rtw_hal_set_hwreg()
1242 usb_write8(Adapter, MSR, val8); in rtw_hal_set_hwreg()
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| /Linux-v5.4/drivers/net/wireless/realtek/rtl818x/ |
| D | rtl818x.h | 185 u8 MSR; member
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